[PATCH v2 2/2] drm/amd: enable S/G for RAVEN chip

[Michel Dänzer]

On 2019-07-23 8:25 p.m., Andrey Grodzovsky wrote:
> From: Shirish S <shirish.s at amd.com>
> 
> enables gpu_vm_support in dm and adds
> AMDGPU_GEM_DOMAIN_GTT as supported domain
> 
> v2:
> Move BO placement logic into amdgpu_display_supported_domains
> 
> Change-Id: If34300beaa60be2d36170b7b5b096ec644502b20
> Signed-off-by: Shirish S <shirish.s at amd.com>
> Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky at amd.com>
> ---
>  [...]
> 
> @@ -498,8 +499,16 @@ uint32_t amdgpu_display_supported_domains(struct amdgpu_device *adev)
>  	uint32_t domain = AMDGPU_GEM_DOMAIN_VRAM;
>  
>  #if defined(CONFIG_DRM_AMD_DC)
> -	if (adev->asic_type >= CHIP_CARRIZO && adev->asic_type < CHIP_RAVEN &&
> -	    adev->flags & AMD_IS_APU &&
> +	/*
> +	 * if drm_arch_can_wc_memory returns false in amdgpu_bo_do_create
> +	 * AMDGPU_GEM_CREATE_CPU_GTT_USWC flag was unset meaning that USWC mappings
> +	 * is not supported for this board. But this mapping is required
> +	 * to avoid hang caused by placement of scanout BO in GTT on certain
> +	 * APUs. So force the BO placement to VRAM in case this architecture
> +	 * will not allow USWC mappings.
> +	 */
> +	if (adev->asic_type >= CHIP_CARRIZO && adev->asic_type <= CHIP_RAVEN &&
> +	    adev->flags & AMD_IS_APU && drm_arch_can_wc_memory() &&
>  	    amdgpu_device_asic_has_dc_support(adev->asic_type))
>  		domain |= AMDGPU_GEM_DOMAIN_GTT;
>  #endif

drm_arch_can_wc_memory() never returns false for an APU. However, it
returning false isn't the only case where AMDGPU_GEM_CREATE_CPU_GTT_USWC
can be cleared, see amdgpu_bo_do_create(). I suggest moving that logic
into a separate helper function which can be used here as well.


-- 
Earthling Michel Dänzer               |              https://www.amd.com
Libre software enthusiast             |             Mesa and X developer