[PATCH 1/3] drm/amdgpu: Fix hard hang for S/G display BOs.
michel at daenzer.net
Wed Jul 24 07:43:32 UTC 2019
On 2019-07-23 7:31 p.m., Grodzovsky, Andrey wrote:
> On 7/23/19 12:18 PM, Michel Dänzer wrote:
>> Anyway, this should be handled in amdgpu_display_supported_domains
>> instead (e.g. by not allowing GTT if CONFIG_X86_32 is defined),
> We have drm_arch_can_wc_memory function to cover all the cases when USWC
> mapping is not allowed, why the CONFIG_X86_32 here ?
It's one case where amdgpu_bo_do_create() clears the
>> otherwise the BO could still be pinned to GTT later.
> The only other later place I know is dm_plane_helper_prepare_fb of which
> I take care in patch 3. What other places you have in mind ?
amdgpu_dma_buf_begin_cpu_access & amdgpu_mode_dumb_create. (While not
handling it there probably won't cause hangs, it'd likely result in
superfluous BO migrations)
But even if there were no other places right now, handling it separately
would be fragile WRT future amdgpu_display_supported_domains callers
getting it wrong.
Anyway, you're attempting to handle it in
amdgpu_display_supported_domains in the v2 series, thanks.
Earthling Michel Dänzer | https://www.amd.com
Libre software enthusiast | Mesa and X developer
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