[PATCH] drm/amd/amdgpu/vcn_v2_0: Set CMD_SOURCE for RB commands
Christian König
ckoenig.leichtzumerken at gmail.com
Thu Jul 25 08:09:30 UTC 2019
Should we have a define for the 0x80000000 somewhere?
And please break the commit log into fewer characters per line.
Apart from that looks good to me,
Christian.
Am 25.07.19 um 00:23 schrieb Liu, Leo:
> Please separate the patches to 2 patches. i. e. New ring test as one
> patch.
>
> Regards,
> Leo
> ------------------------------------------------------------------------
> *From:* amd-gfx <amd-gfx-bounces at lists.freedesktop.org> on behalf of
> Thai, Thong <Thong.Thai at amd.com>
> *Sent:* July 24, 2019 3:50:47 PM
> *To:* amd-gfx at lists.freedesktop.org <amd-gfx at lists.freedesktop.org>
> *Subject:* [PATCH] drm/amd/amdgpu/vcn_v2_0: Set CMD_SOURCE for RB
> commands
> Sets the CMD_SOURCE bit for VCN 2.0 decoder ring-buffer commands. This
> bit was previously set by the RBC HW on older versions of the
> firmware, and now needs to be set by the driver in order to work with
> the SW RBC found in newer versions of the firmware.
>
> Signed-off-by: Thong Thai <thong.thai at amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c | 44 ++++++++++++++++++++++-----
> 1 file changed, 37 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
> b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
> index bc9726787c97..8daee23425f8 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
> @@ -1488,7 +1488,7 @@ static void
> vcn_v2_0_dec_ring_insert_start(struct amdgpu_ring *ring)
> amdgpu_ring_write(ring,
> PACKET0(mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET, 0));
> amdgpu_ring_write(ring, 0);
> amdgpu_ring_write(ring,
> PACKET0(mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET, 0));
> - amdgpu_ring_write(ring, VCN_DEC_CMD_PACKET_START << 1);
> + amdgpu_ring_write(ring, 0x80000000 | (VCN_DEC_CMD_PACKET_START
> << 1));
> }
>
> /**
> @@ -1501,7 +1501,7 @@ static void
> vcn_v2_0_dec_ring_insert_start(struct amdgpu_ring *ring)
> static void vcn_v2_0_dec_ring_insert_end(struct amdgpu_ring *ring)
> {
> amdgpu_ring_write(ring,
> PACKET0(mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET, 0));
> - amdgpu_ring_write(ring, VCN_DEC_CMD_PACKET_END << 1);
> + amdgpu_ring_write(ring, 0x80000000 | (VCN_DEC_CMD_PACKET_END
> << 1));
> }
>
> /**
> @@ -1546,7 +1546,7 @@ static void vcn_v2_0_dec_ring_emit_fence(struct
> amdgpu_ring *ring, u64 addr, u64
> amdgpu_ring_write(ring, upper_32_bits(addr) & 0xff);
>
> amdgpu_ring_write(ring,
> PACKET0(mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET, 0));
> - amdgpu_ring_write(ring, VCN_DEC_CMD_FENCE << 1);
> + amdgpu_ring_write(ring, 0x80000000 | (VCN_DEC_CMD_FENCE << 1));
>
> amdgpu_ring_write(ring,
> PACKET0(mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET, 0));
> amdgpu_ring_write(ring, 0);
> @@ -1556,7 +1556,7 @@ static void vcn_v2_0_dec_ring_emit_fence(struct
> amdgpu_ring *ring, u64 addr, u64
>
> amdgpu_ring_write(ring,
> PACKET0(mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET, 0));
>
> - amdgpu_ring_write(ring, VCN_DEC_CMD_TRAP << 1);
> + amdgpu_ring_write(ring, 0x80000000 | (VCN_DEC_CMD_TRAP << 1));
> }
>
> /**
> @@ -1600,7 +1600,7 @@ static void
> vcn_v2_0_dec_ring_emit_reg_wait(struct amdgpu_ring *ring,
>
> amdgpu_ring_write(ring,
> PACKET0(mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET, 0));
>
> - amdgpu_ring_write(ring, VCN_DEC_CMD_REG_READ_COND_WAIT << 1);
> + amdgpu_ring_write(ring, 0x80000000 |
> (VCN_DEC_CMD_REG_READ_COND_WAIT << 1));
> }
>
> static void vcn_v2_0_dec_ring_emit_vm_flush(struct amdgpu_ring *ring,
> @@ -1629,7 +1629,7 @@ static void vcn_v2_0_dec_ring_emit_wreg(struct
> amdgpu_ring *ring,
>
> amdgpu_ring_write(ring,
> PACKET0(mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET, 0));
>
> - amdgpu_ring_write(ring, VCN_DEC_CMD_WRITE_REG << 1);
> + amdgpu_ring_write(ring, 0x80000000 | (VCN_DEC_CMD_WRITE_REG <<
> 1));
> }
>
> /**
> @@ -2082,6 +2082,36 @@ static int vcn_v2_0_process_interrupt(struct
> amdgpu_device *adev,
> return 0;
> }
>
> +int vcn_v2_0_dec_ring_test_ring(struct amdgpu_ring *ring)
> +{
> + struct amdgpu_device *adev = ring->adev;
> + uint32_t tmp = 0;
> + unsigned i;
> + int r;
> +
> + WREG32(adev->vcn.external.scratch9, 0xCAFEDEAD);
> + r = amdgpu_ring_alloc(ring, 3);
> + if (r)
> + return r;
> + amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0));
> + amdgpu_ring_write(ring, 0x80000000 | (VCN_DEC_CMD_PACKET_START
> << 1));
> + amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.scratch9, 0));
> + amdgpu_ring_write(ring, 0xDEADBEEF);
> + amdgpu_ring_commit(ring);
> + for (i = 0; i < adev->usec_timeout; i++) {
> + tmp = RREG32(adev->vcn.external.scratch9);
> + if (tmp == 0xDEADBEEF)
> + break;
> + DRM_UDELAY(1);
> + }
> +
> + if (i >= adev->usec_timeout)
> + r = -ETIMEDOUT;
> +
> + return r;
> +}
> +
> +
> static int vcn_v2_0_set_powergating_state(void *handle,
> enum amd_powergating_state
> state)
> {
> @@ -2145,7 +2175,7 @@ static const struct amdgpu_ring_funcs
> vcn_v2_0_dec_ring_vm_funcs = {
> .emit_ib = vcn_v2_0_dec_ring_emit_ib,
> .emit_fence = vcn_v2_0_dec_ring_emit_fence,
> .emit_vm_flush = vcn_v2_0_dec_ring_emit_vm_flush,
> - .test_ring = amdgpu_vcn_dec_ring_test_ring,
> + .test_ring = vcn_v2_0_dec_ring_test_ring,
> .test_ib = amdgpu_vcn_dec_ring_test_ib,
> .insert_nop = vcn_v2_0_dec_ring_insert_nop,
> .insert_start = vcn_v2_0_dec_ring_insert_start,
> --
> 2.17.1
>
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