[PATCH v5 0/4] Enable S/G for Picasso

Andrey Grodzovsky andrey.grodzovsky at amd.com
Thu Jul 25 14:24:39 UTC 2019

First patches fixes a hard hang introduced by placing the display BO in 
GTT memory because of HW issues with cached mappings. Second patch does
some minor reafactoring to resue code in thrid patch. Third patch adds
check for USWC support as condition to placing APUs scanout BO in GTT.
Last patch enables S/G.

Andrey Grodzovsky (3):
  drm/amdgpu: Fix hard hang for S/G display BOs.
  drm/amdgpu: Create helper to clear AMDGPU_GEM_CREATE_CPU_GTT_USWC
  drm/amdgpu: Add check for USWC support for

Shirish S (1):
  drm/amd/display: enable S/G for RAVEN chip

 drivers/gpu/drm/amd/amdgpu/amdgpu_display.c       | 11 +++-
 drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c            |  7 ++-
 drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c           |  3 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_object.c        | 61 +++++++++++++----------
 drivers/gpu/drm/amd/amdgpu/amdgpu_object.h        |  2 +
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c |  2 +-
 6 files changed, 52 insertions(+), 34 deletions(-)


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