[PATCH v2] drm/amd/display: Use switch table for dc_to_smu_clock_type

[Kazlauskas, Nicholas]

On 7/25/19 1:57 PM, sunpeng.li at amd.com wrote:
> From: Leo Li <sunpeng.li at amd.com>
> 
> Using a static int array will cause errors if the given dm_pp_clk_type
> is out-of-bounds. For robustness, use a switch table, with a default
> case to handle all invalid values.
> 
> v2: 0 is a valid clock type for smu_clk_type. Return SMU_CLK_COUNT
>      instead on invalid mapping.
> 
> Signed-off-by: Leo Li <sunpeng.li at amd.com>

Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas at amd.com>

> ---
>   .../amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c  | 37 +++++++++++++------
>   1 file changed, 25 insertions(+), 12 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
> index 20e82c9f6d67..e52dde21610f 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
> @@ -152,18 +152,31 @@ static void get_default_clock_levels(
>   static enum smu_clk_type dc_to_smu_clock_type(
>   		enum dm_pp_clock_type dm_pp_clk_type)
>   {
> -#define DCCLK_MAP_SMUCLK(dcclk, smuclk) \
> -	[dcclk] = smuclk
> -
> -	static int dc_clk_type_map[] = {
> -		DCCLK_MAP_SMUCLK(DM_PP_CLOCK_TYPE_DISPLAY_CLK,	SMU_DISPCLK),
> -		DCCLK_MAP_SMUCLK(DM_PP_CLOCK_TYPE_ENGINE_CLK,	SMU_GFXCLK),
> -		DCCLK_MAP_SMUCLK(DM_PP_CLOCK_TYPE_MEMORY_CLK,	SMU_MCLK),
> -		DCCLK_MAP_SMUCLK(DM_PP_CLOCK_TYPE_DCEFCLK,	SMU_DCEFCLK),
> -		DCCLK_MAP_SMUCLK(DM_PP_CLOCK_TYPE_SOCCLK,	SMU_SOCCLK),
> -	};
> -
> -	return dc_clk_type_map[dm_pp_clk_type];
> +	enum smu_clk_type smu_clk_type = SMU_CLK_COUNT;
> +
> +	switch (dm_pp_clk_type) {
> +	case DM_PP_CLOCK_TYPE_DISPLAY_CLK:
> +		smu_clk_type = SMU_DISPCLK;
> +		break;
> +	case DM_PP_CLOCK_TYPE_ENGINE_CLK:
> +		smu_clk_type = SMU_GFXCLK;
> +		break;
> +	case DM_PP_CLOCK_TYPE_MEMORY_CLK:
> +		smu_clk_type = SMU_MCLK;
> +		break;
> +	case DM_PP_CLOCK_TYPE_DCEFCLK:
> +		smu_clk_type = SMU_DCEFCLK;
> +		break;
> +	case DM_PP_CLOCK_TYPE_SOCCLK:
> +		smu_clk_type = SMU_SOCCLK;
> +		break;
> +	default:
> +		DRM_ERROR("DM_PPLIB: invalid clock type: %d!\n",
> +			  dm_pp_clk_type);
> +		break;
> +	}
> +
> +	return smu_clk_type;
>   }
>   
>   static enum amd_pp_clock_type dc_to_pp_clock_type(
>