[PATCH] drm/amdgpu/display: fix the build without CONFIG_DRM_AMD_DC_DSC_SUPPORT

[Kazlauskas, Nicholas]

On 7/26/19 12:09 PM, Alex Deucher wrote:
> Some code was missing the CONFIG_DRM_AMD_DC_DSC_SUPPORT guard.
> 
> Signed-off-by: Alex Deucher <alexander.deucher at amd.com>

Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas at amd.com>

We probably want to drop this and the DCN2 guard eventually though.

Nicholas Kazlauskas

> ---
>   drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c | 2 ++
>   1 file changed, 2 insertions(+)
> 
> diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
> index 69e4d0d96c7f..38b3c89b2a59 100644
> --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
> +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
> @@ -630,9 +630,11 @@ static void dcn20_init_hw(struct dc *dc)
>   		}
>   	}
>   
> +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
>   	/* Power gate DSCs */
>   	for (i = 0; i < res_pool->res_cap->num_dsc; i++)
>   		dcn20_dsc_pg_control(hws, res_pool->dscs[i]->inst, false);
> +#endif
>   
>   	/* Blank pixel data with OPP DPG */
>   	for (i = 0; i < dc->res_pool->timing_generator_count; i++) {
>