[PATCH] drm/amdgpu: Update pitch on page flips without DC as well

Deucher, Alexander Alexander.Deucher at amd.com
Mon Jul 29 16:21:33 UTC 2019


Reviewed-by: Alex Deucher <alexander.deucher at amd.com>
________________________________
From: amd-gfx <amd-gfx-bounces at lists.freedesktop.org> on behalf of Michel Dänzer <michel at daenzer.net>
Sent: Monday, July 29, 2019 12:20 PM
To: amd-gfx at lists.freedesktop.org <amd-gfx at lists.freedesktop.org>
Subject: [PATCH] drm/amdgpu: Update pitch on page flips without DC as well

From: Michel Dänzer <michel.daenzer at amd.com>

DC already handles this correctly since amdgpu minor version 31. Bump
the minor version again so that xf86-video-amdgpu can take advantage of
this working without DC as well now.

Signed-off-by: Michel Dänzer <michel.daenzer at amd.com>
---

See https://gitlab.freedesktop.org/xorg/driver/xf86-video-amdgpu/merge_requests/39
for the corresponding xf86-video-amdgpu change.

 drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 3 ++-
 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c  | 4 ++++
 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c  | 4 ++++
 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c   | 4 ++++
 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c   | 4 ++++
 5 files changed, 18 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index 800d0ceb14b4..cf334c465805 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -77,9 +77,10 @@
  * - 3.31.0 - Add support for per-flip tiling attribute changes with DC
  * - 3.32.0 - Add syncobj timeline support to AMDGPU_CS.
  * - 3.33.0 - Fixes for GDS ENOMEM failures in AMDGPU_CS.
+ * - 3.34.0 - Non-DC can flip correctly between buffers with different pitches
  */
 #define KMS_DRIVER_MAJOR        3
-#define KMS_DRIVER_MINOR       33
+#define KMS_DRIVER_MINOR       34
 #define KMS_DRIVER_PATCHLEVEL   0

 #define AMDGPU_MAX_TIMEOUT_PARAM_LENTH  256
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
index 1f0426d2fc2a..c609b7af0b6b 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
@@ -233,6 +233,7 @@ static void dce_v10_0_page_flip(struct amdgpu_device *adev,
                                 int crtc_id, u64 crtc_base, bool async)
 {
         struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
+       struct drm_framebuffer *fb = amdgpu_crtc->base.primary->fb;
         u32 tmp;

         /* flip at hsync for async, default is vsync */
@@ -240,6 +241,9 @@ static void dce_v10_0_page_flip(struct amdgpu_device *adev,
         tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL,
                             GRPH_SURFACE_UPDATE_H_RETRACE_EN, async ? 1 : 0);
         WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
+       /* update pitch */
+       WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset,
+              fb->pitches[0] / fb->format->cpp[0]);
         /* update the primary scanout address */
         WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
                upper_32_bits(crtc_base));
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
index 2280b971d758..719db058b306 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
@@ -251,6 +251,7 @@ static void dce_v11_0_page_flip(struct amdgpu_device *adev,
                                 int crtc_id, u64 crtc_base, bool async)
 {
         struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
+       struct drm_framebuffer *fb = amdgpu_crtc->base.primary->fb;
         u32 tmp;

         /* flip immediate for async, default is vsync */
@@ -258,6 +259,9 @@ static void dce_v11_0_page_flip(struct amdgpu_device *adev,
         tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL,
                             GRPH_SURFACE_UPDATE_IMMEDIATE_EN, async ? 1 : 0);
         WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
+       /* update pitch */
+       WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset,
+              fb->pitches[0] / fb->format->cpp[0]);
         /* update the scanout addresses */
         WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
                upper_32_bits(crtc_base));
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
index bea32f076b91..8ee99651d01a 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
@@ -186,10 +186,14 @@ static void dce_v6_0_page_flip(struct amdgpu_device *adev,
                                int crtc_id, u64 crtc_base, bool async)
 {
         struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
+       struct drm_framebuffer *fb = amdgpu_crtc->base.primary->fb;

         /* flip at hsync for async, default is vsync */
         WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, async ?
                GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_H_RETRACE_EN_MASK : 0);
+       /* update pitch */
+       WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset,
+              fb->pitches[0] / fb->format->cpp[0]);
         /* update the scanout addresses */
         WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
                upper_32_bits(crtc_base));
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
index 13da915991dd..7037e016493c 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
@@ -181,10 +181,14 @@ static void dce_v8_0_page_flip(struct amdgpu_device *adev,
                                int crtc_id, u64 crtc_base, bool async)
 {
         struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
+       struct drm_framebuffer *fb = amdgpu_crtc->base.primary->fb;

         /* flip at hsync for async, default is vsync */
         WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, async ?
                GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_H_RETRACE_EN_MASK : 0);
+       /* update pitch */
+       WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset,
+              fb->pitches[0] / fb->format->cpp[0]);
         /* update the primary scanout addresses */
         WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
                upper_32_bits(crtc_base));
--
2.22.0

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