[PATCH 1/2] drm/amd/powerplay: add set_power_profile_mode for raven1_refresh

[Quan, Evan]

Reviewed-by: Evan Quan <evan.quan at amd.com>

> -----Original Message-----
> From: amd-gfx <amd-gfx-bounces at lists.freedesktop.org> On Behalf Of
> Prike Liang
> Sent: 2019年5月31日 21:11
> To: amd-gfx at lists.freedesktop.org
> Cc: Deucher, Alexander <Alexander.Deucher at amd.com>; Huang, Ray
> <Ray.Huang at amd.com>; Gui, Jack <Jack.Gui at amd.com>
> Subject: [PATCH 1/2] drm/amd/powerplay: add set_power_profile_mode
> for raven1_refresh
> 
> From: Chengming Gui <Jack.Gui at amd.com>
> 
> add gfxoff_state_changed_by_workload to control gfxoff when set
> power_profile_mode
> 
> Signed-off-by: Chengming Gui <Jack.Gui at amd.com>
> ---
>  drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c       |  1 +
>  drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c | 31
> ++++++++++++++++++++---
>  drivers/gpu/drm/amd/powerplay/inc/hwmgr.h         |  1 +
>  3 files changed, 30 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
> b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
> index 6cd6497..f1d326c 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
> @@ -92,6 +92,7 @@ int hwmgr_early_init(struct pp_hwmgr *hwmgr)
>  	hwmgr_set_user_specify_caps(hwmgr);
>  	hwmgr->fan_ctrl_is_in_default_mode = true;
>  	hwmgr_init_workload_prority(hwmgr);
> +	hwmgr->gfxoff_state_changed_by_workload = false;
> 
>  	switch (hwmgr->chip_family) {
>  	case AMDGPU_FAMILY_CI:
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
> b/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
> index 9a595f7..e32ae9d 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
> @@ -1258,21 +1258,46 @@ static int
> smu10_get_power_profile_mode(struct pp_hwmgr *hwmgr, char *buf)
>  	return size;
>  }
> 
> +static bool smu10_is_raven1_refresh(struct pp_hwmgr *hwmgr) {
> +	struct amdgpu_device *adev = hwmgr->adev;
> +	if ((adev->asic_type == CHIP_RAVEN) &&
> +	    (adev->rev_id != 0x15d8) &&
> +	    (hwmgr->smu_version >= 0x41e2b))
> +		return true;
> +	else
> +		return false;
> +}
> +
>  static int smu10_set_power_profile_mode(struct pp_hwmgr *hwmgr, long
> *input, uint32_t size)  {
>  	int workload_type = 0;
> +	int result = 0;
> 
>  	if (input[size] > PP_SMC_POWER_PROFILE_COMPUTE) {
>  		pr_err("Invalid power profile mode %ld\n", input[size]);
>  		return -EINVAL;
>  	}
> -	hwmgr->power_profile_mode = input[size];
> +	if (hwmgr->power_profile_mode == input[size])
> +		return 0;
> 
>  	/* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
>  	workload_type =
> -		conv_power_profile_to_pplib_workload(hwmgr-
> >power_profile_mode);
> -	smum_send_msg_to_smc_with_parameter(hwmgr,
> PPSMC_MSG_ActiveProcessNotify,
> +		conv_power_profile_to_pplib_workload(input[size]);
> +	if (workload_type &&
> +	    smu10_is_raven1_refresh(hwmgr) &&
> +	    !hwmgr->gfxoff_state_changed_by_workload) {
> +		smu10_gfx_off_control(hwmgr, false);
> +		hwmgr->gfxoff_state_changed_by_workload = true;
> +	}
> +	result = smum_send_msg_to_smc_with_parameter(hwmgr,
> +PPSMC_MSG_ActiveProcessNotify,
>  						1 << workload_type);
> +	if (!result)
> +		hwmgr->power_profile_mode = input[size];
> +	if (workload_type && hwmgr->gfxoff_state_changed_by_workload)
> {
> +		smu10_gfx_off_control(hwmgr, true);
> +		hwmgr->gfxoff_state_changed_by_workload = false;
> +	}
> 
>  	return 0;
>  }
> diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
> b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
> index bac3d85..c92999a 100644
> --- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
> +++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
> @@ -782,6 +782,7 @@ struct pp_hwmgr {
>  	uint32_t workload_mask;
>  	uint32_t workload_prority[Workload_Policy_Max];
>  	uint32_t workload_setting[Workload_Policy_Max];
> +	bool gfxoff_state_changed_by_workload;
>  };
> 
>  int hwmgr_early_init(struct pp_hwmgr *hwmgr);
> --
> 2.7.4
> 
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