[PATCH 000/459] amdgpu support for Navi10
Alex Deucher
alexdeucher at gmail.com
Mon Jun 17 19:26:44 UTC 2019
Hi,
This patch set adds support for Navi10 asics to amdgpu. This includes
support for:
- Core driver support
- Displays (DCN2)
- GFX and compute (GFX10)
- System DMA (SDMA 5)
- Multimedia decode and encode (VCN2)
- Power management
The new register headers are huge, so I have not sent them out. You can find
the full patch series here:
https://cgit.freedesktop.org/~agd5f/linux/log/?h=amd-staging-drm-next-navi10
LLVM changes are already working their way upstream and mesa changes (OpenGL and
Multmedia) will be available shortly.
Aidan Wood (2):
drm/amd/display: Properly set DCF clock
drm/amd/display: Properly set u clock
Alex Deucher (15):
drm/amdkfd: Introduce DIQ type mqd manager for gfx10
drm/amdkfd: Add mqd size in mqd manager struct for gfx10
drm/amdkfd: Allocate hiq and sdma mqd from mqd trunk for gfx10
drm/amdkfd: Introduce XGMI SDMA queue type for gfx10
drm/amdkfd: Delete alloc_format field from map_queue struct for gfx10
drm/amdkfd: update gfx10 support for latest kfd changes
drm/amdkfd: add more navi10 pci ids
drm/amdgpu: add Navi10 pci ids
drm/amd/powerplay/smu11: remove smu_update_table_with_arg
drm/amdgpu/powerplay: add license to smu11 header
drm/amdgpu/powerplay/vega20: use correct table index
drm/amdgpu/gfx10: update to latest golden setting
drm/amd/display: add fast_validate parameter to
dcn20_validate_bandwidth
drm/amd/display: updates for dcn20_update_bandwidth
drm/amd/display: update dcn2 dc_plane_cap
Anthony Koo (1):
drm/amd/display: do not power on eDP power rail early
Aric Cyr (1):
drm/amd/display: Intermittent DCN2 pipe hang on mode change
Bob Yang (1):
drm/amd/display: fixed DCC corruption
Charlene Liu (13):
drm/amd/display: dcn2 dmcu wait_for_loop update with dispclk.
drm/amd/display: fix can not turn on two displays due to DSC_RESOURCE
failed.
drm/amd/display: Add hubp_init entry to hubp vtable
drm/amd/display: add SW_USE_I2C_REG request.
drm/amd/display: Create DWB resource for DCN2
drm/amd/display: [backport] dwb dm + efc support
drm/amd/display: used optimum VSTARTUP instead of MaxVStartup
drm/amd/display: Return UPDATE_TYPE_FULL on writeback update
drm/amd/display: add some parameters to validate bandwidth functions
drm/amd/display: add dwb stere caps and version
drm/amd/display: add p010 and ayuv plane caps
drm/amd/display: dcn2 use fixed clocks.
drm/amd/display: expose dentist_get_did_from_divider
Chris Park (1):
drm/amd/display: Move link functions from dc to dc_link
Christian König (1):
drm/amdgpu: disable concurrent flushes for Navi10 v2
Dmytro Laktyushkin (9):
drm/amd/display: clean up validation failure log spam
drm/amd/display: fix dsc validation
drm/amd/display: fix fpga fclk programming
drm/amd/display: fix dcn2 mpc split decision
drm/amd/display: fix odm mpo disable
drm/amd/display: fix macro_tile_size for tiling
drm/amd/display: add null checks and set update flags for DCN2
drm/amd/display: move vmid determination logic to a module
drm/amd/display: add missing mod_vmid destructor
Eric Bernstein (3):
drm/amd/display: Refactor DIO stream encoder
drm/amd/display: Alpha plane type
drm/amd/display: expose enable dp output functions
Eric Yang (1):
drm/amd/display: Refactor clk_mgr functions
Eryk Brol (2):
drm/amd/display: Ensure DRR triggers in BP
drm/amd/display: Change DCN2 vupdate start programming
Harry Wentland (23):
drm/amd/display: Read soc_bounding_box from gpu_info (v2)
drm/amd/display: Add DCN2 and NV ASIC ID
drm/amd/display: add AUX and I2C for DCN2
drm/amd/display: Add GPIO support for DCN2
drm/amd/display: Add DCN2 BIOS parsing
drm/amd/display: Add DCN2 IRQ handling
drm/amd/display: Add DCN2 changes to DML
drm/amd/display: Add DCN2 DIO
drm/amd/display: Add DCN2 clk mgr
drm/amd/display: Add DCN2 OPTC
drm/amd/display: Add DCN2 OPP
drm/amd/display: Add DCN2 MPC
drm/amd/display: Add DCN2 DPP
drm/amd/display: Add DCN2 HUBP and HUBBUB
drm/amd/display: Add DCN2 MMHUBBUB
drm/amd/display: Add DCN2 DWB
drm/amd/display: Add DCN2 IPP
drm/amd/display: Add DCN2 VMID
drm/amd/display: Add DCN2 HW Sequencer and Resource
drm/amd/display: Add DC core changes for DCN2
drm/amd/display: Hook DCN2 into amdgpu_dm and expose as config (v2)
drm/amdgpu: Enable DC support for Navi10
drm/amd/display: Add DSC support for Navi (v2)
Hawking Zhang (82):
drm/amdgpu: add ATHUB 2.0 register headers
drm/amdgpu: add CLK 11.0 register headers
drm/amdgpu: add DCN 2.0 register headers
drm/amdgpu: add HDP 5.0 register headers
drm/amdgpu: add MP 11.0 register headers
drm/amdgpu: add NBIO 2.3 register headers
drm/amdgpu: add VCN 2.0 register headers
drm/amdgpu: add GC 10.1 register headers (v4)
drm/amdgpu: add MMHUB 2.0 register headers
drm/amdgpu: add OSS 5.0 register headers
drm/amdgpu: add SMUIO 11.0 register headers
drm/amdgpu: add navi10 enums header
drm/amdgpu: atomfirmware.h updates for navi10
drm/amdgpu: add doorbell assignement for navi10
drm/amdgpu: add navi10 ip offset header
drm/amdgpu: Add GDDR6 in vram_name arrary
drm/amdgpu: add gfx10 specific config in amdgpu_gfx_config
drm/amdgpu: add gfx10 specific new member pa_sc_tile_steering_override
drm/amdgpu: add gpu_info_firmware v1_1 structure for navi10
drm/amdgpu: parse the new members added by gpu_info ucode v1_1
drm/amdgpu: add sdma v5 packet header file
drm/amdgpu: add navi pm4 header
drm/amdgpu: query vram type from atomfirmware vram_info
drm/amdgpu: query vram_width from vram_info table
drm/amdgpu: add nbio v2.3 for navi10 (v3)
drm/amdgpu/gfx10: new approach to load pfp fw (v4)
drm/amdgpu/gfx10: new approach to load ce fw (v4)
drm/amdgpu/gfx10: new approach to load gfx10 me fw (v4)
drm/amdgpu: add members in amdgpu_me for gfx queue
drm/amdgpu: acquire available gfx queues
drm/amdgpu: add helper function for gfx queue/bitmap transition
drm/amdgpu: rename amdgpu_gfx_compute_mqd_sw_init
drm/amdgpu: Move common code to amdgpu_gfx.c
drm/amdgpu: enable gfx eop interrupt per gfx pipe
drm/amdgpu: add module parameter for async_gfx_ring enablement
drm/amdgpu: create mqd for gfx queues on navi10
drm/amdgpu: add new HDP CG flags
drm/amdgpu: add flag to support IH clock gating
drm/amdgpu: correct pte mtype field for navi
drm/amd/gmc9: rename AMDGPU_PTE_MTYPE to AMDGPU_PTE_MTYPE_VG10
drm/amdgpu: add gfxhub v2.0 block for navi10 (v4)
drm/amdgpu: add mmhub v2 block for navi10 (v4)
drm/amdgpu: add gmc v10 ip block for navi10 (v6)
drm/amdgpu: add irq sources for gfx v10_1
drm/amdgpu: add irq sources for sdma v5_0
drm/amdgpu: add irq sources for vcn v2_0 (v2)
drm/amd/display: move dcn v1_0 irq source header to ivsrcid/dcn/
drm/amdgpu: add navi10 ih ip block (v3)
drm/amdgpu: add structure to support build-in toc to psp sos
drm/amdgpu/psp: support init psp sos microcode with build-in toc
drm/amdgpu: use rlc toc from psp sos binary
drm/amdgpu: rename rlc autoload to backdoor autoload
drm/amdgpu: add helper function to print psp hdr
drm/amdgpu/psp: print out psp v11 ucode hdr in drm debug mode
drm/amdgpu/psp: support print out psp firmware header v1_1 info
drm/amdgpu/psp: add structure to support load toc in psp (v2)
drm/amdgpu/psp: add support to load TOC to psp
drm/amdgpu/psp: start rlc autoload after psp recieved all gfx firmware
drm/amdgpu/psp: switch to use sos_offset_bytes member as sys_bin_size
drm/amdgpu/psp: perform tmr_init and asd_init after loading sysdrv/sos
drm/amdgpu/psp: update psp gfx interface to match with psp fw (v2)
drm/amdgpu/psp: initialize autoload_supported flag in psp_sw_init
drm/amd/amdgpu: add flag to mark whether autoload is supported or not
drm/amdgpu/psp: skip mec jt when autoload is enabled
drm/amdgpu: enable psp front door loading by default on navi10
drm/amdgpu: declare navi10 asd firmware
drm/amdgpu/psp11: skip ta firmware for navi10
drm/amdgpu: add pa_sc_tile_steering_override to drm_amdgpu_info_device
drm/amdgpu: set the default value of pa_sc_tile_steering_override
drm/amdgpu: add initial support for sdma v5.0 (v6)
drm/amdgpu: add gfx v10 implementation (v8)
drm/amdgpu: avoid to use SOC15_REG_OFFSET in static array for navi10
drm/amdgpu: add navi10 common ip block (v3)
drm/amdgpu: Add navi10 kfd support for amdgpu (v3)
drm/amdgpu: update golden setting programming logic
drm/amdgpu: enable sw smu driver for navi10 by default
drm/amd/powerplay: remove uvd_gated/vce_gated from smu_power_context
(v2)
drm/amdgpu/gfx10: remove static GDS, GWS and OA allcoation
drm/amd/powerplay: move get_thermal_temperature_range to ppt funcs
drm/amd/powerplay: fix no statements in fucntion returning non-void
drm/amdgpu: initialize THM & CLK IP registers base address
drm/amd/display: enable DSC support by default
Huang Rui (39):
drm/amdgpu: add navi10 asic type
drm/amdgpu: add NV series gpu family id
drm/amdgpu: add GDDR6 vram type
drm/amdgpu: add navi10 gpu info firmware
drm/amdgpu: add v10 structs header (v2)
drm/amdgpu: add gfx v10 clear state header v2
drm/amdgpu: set navi10's fw loading type as direct
drm/amdgpu: load smc ucode at first with psp while rlc auto load is
supported
drm/amdgpu: add to set navi ip blocks
drm/amd/powerplay: update smu v11 ppsmc header
drm/amd/powerplay: update smu 11 driver if header for navi10
drm/amd/powerplay: fix the mp/smuio header for navi10
drm/amd/powerplay: introduce the navi10 pptable implementation
drm/amd/powerplay: set smu v11 funcs for navi10
drm/amd/powerplay: add navi10 smc ucode init and navi10 ppt functions
setting
drm/amd/powerplay: move bootup value before read pptable from vbios
drm/amd/powerplay: update smu11 driver if header for navi10 (v2)
drm/amdgpu: bump smc firmware header version to v2 (v2)
drm/amdgpu: fix the issue of checking on message mapping
drm/amd/powerplay: smu needs to be initialized after rlc in direct
mode
drm/amd/powerplay: introduce the function to load the soft pptable for
navi10 (v2)
drm/amd/powerplay: modify the feature mask to enable gfx/soc dpm
drm/amd/powerplay: skip od feature on navi10 for the moment
drm/amd/powerplay: introduce smu clk type to handle ppclk for each
asic
drm/amd/powerplay: introduce smu feature type to handle feature mask
for each asic
drm/amd/powerplay: introduce smu table id type to handle the smu table
for each asic
drm/amd/powerplay: init table_count for smu tables on asic level
drm/amd/powerplay: add tables_init interface for each asic
drm/amd/powerplay: modify smu_update_table to use SMU_TABLE_xxx as the
input
drm/amd/powerplay: use the table size member in the structure instead
of getting directly
drm/amd/powerplay: move PPTable_t uses into asic level
drm/amd/powerplay: move SmuMetrics_t uses into asic level
drm/amd/powerplay: move Watermarks_t uses into asic level
drm/amd/powerplay: introduce smu power source type to handle AC/DC
source for each asic
drm/amd/powerplay: move getting MAX_FAN_RPM value to asic level
drm/amd/powerplay: don't include the smu11 driver if header in smu v11
(v2)
drm/amd/powerplay: do not set dpm_enabled flag before VCN/DCN DPM is
workable
drm/amdgpu: mask some pm interfaces for navi10 because they are
changed or not workable so far
drm/amd/powerplay: set dpm_enabled flag but don't enable vcn dpm
Ilya Bakoulin (7):
drm/amd/display: Add writeback_config to VBA vars
drm/amd/display: Fix DCFCLK and SOCCLK not set
drm/amd/display: Fix ODM combine data format
drm/amd/display: Fix LB BPP and Cursor width
drm/amd/display: Drive-by fixes for display_mode_vba
drm/amd/display: Fix incorrect DML output_bpp value
drm/amd/display: Fix incorrect vba type
Jack Xiao (48):
drm/amdgpu/gfx10: add special unmap_queues packet for preemption
drm/amdgpu: enable async gfx ring by default
drm/amdgpu/athub2: enable athub2 clock gating
drm/amdgpu: refine the PTE encoding of PRT for navi10
drm/amdgpu: add the trailing fence per ring
drm/amdgpu: add mcbp driver parameter
drm/amdgpu: enable the static csa when mcbp enabled
drm/amdgpu: add ib preemption status in amdgpu_job
drm/amdgpu/sdma: allocate CSA per sdma ring
drm/amdgpu: program for resuming preempted ib
drm/amdgpu: add mcbp unit test in debugfs (v2)
drm/amdgpu: mark the partial job as preempted in mcbp unit test
drm/amdgpu/mes: add amdgpu_mes driver parameter
drm/amdgpu/mes: add mes header file and definition
drm/amdgpu/mes: add definitions of ip callback function
drm/amdgpu/mes: enable mes on navi10 and later asic
drm/amdgpu/mes10.1: add ip block mes10.1 (v2)
drm/amdgpu/gfx10: fix issues for suspend/resume
drm/amdgpu/vcn2: notify SMU power up/down VCN
drm/amdgpu/vcn2: don't access register when power gated
drm/amdgpu: enable vcn dpm scheme for navi
drm/amdgpu/nv: set vcn pg flag
drm/amdgpu: fix memory leak in preemption unit test
drm/amdgpu/gfx10: adjust GDS backup size according to real size
drm/amdgpu/sdma5: incorrect variable type for gpu address
drm/amdgpu/ucode: add the definitions of MES ucode and ucode data
drm/amdgpu/ucode: add mes firmware file support
drm/amdgpu/mes10.1: add mes firmware info fields
drm/amdgpu/mes10.1: load mes firmware file to CPU buffer
drm/amdgpu/mes10.1: implement ucode CPU buffer destruction
drm/amdgpu/mes10.1: upload mes ucode to gpu buffer
drm/amdgpu/mes10.1: upload mes data ucode to gpu buffer
drm/amdgpu/mes10.1: implement ucode buffers destruction
drm/amdgpu/mes10.1: implement MES firmware backdoor loading
drm/amdgpu/mes10.1: implement mes enablement function
drm/amdgpu/mes10.1: enable mes FW backdoor loading
drm/amd/powerplay/smu11: disable PLL shutdown when gfxoff enabled
drm/amdgpu: RLC must be disabled after SMU when S3 on navi
drm/amdgpu/gfx10: remove unnecessary waiting on gfx inactive
drm/amdgpu/gfx10: require to pin/unpin CSIB BO when suspend/resume
drm/amd: the data retured from PRT is expected to be 0
drm/amdgpu/psp: add new VCN RAM ucode id to psp
drm/amdgpu: add corresponding vcn ram ucode id
drm/amdgpu/psp: convert ucode id to psp ucode id
drm/amdgpu/psp: add new psp interface for vcn updating sram
drm/amd/powerplay: update smu11_driver_if_navi10.h
drm/amd/powerplay: disable fw dstate when gfxoff is enabled
drm/amd/powerplay: enable BACO feature as WAR
Joshua Aberback (6):
drm/amd/display: Program VTG params after programming Global Sync for
DCN2
drm/amd/display: Remove dependency on pipe->plane for immedaite flip
status
drm/amd/display: Optimize bandwidth validation by adding early return
drm/amd/display: Add profiling tools for bandwidth validation
drm/amd/display: Remove OPP clock programming on plane disable
drm/amd/display: Set test pattern on blank when using Visual Confirm
Josip Pavic (1):
drm/amd/display: enable abm on dcn2
Jun Lei (7):
drm/amd/display: update calculated bounding box logic for NV
drm/amd/display: fix pstate allow handling in dcn2
drm/amd/display: always use 4 dp lanes for dml
drm/amd/display: Add missing VM conversion from hw values
drm/amd/display: add support for forcing DCFCLK without affecting
watermarks
drm/amd/display: making DCN20 WM table non-overlapping
drm/amd/display: update DCN2 uclk switch time
Kenneth Feng (15):
drm/amd/powerplay: enable backdoor smu fw loading (v2)
drm/amd/powerplay: enable power features
drm/amd: add gfxoff support on navi10
drm/amd/amdgpu: fw version check with gfxoff
drm/amd/powerplay: gfxoff-seperate the Vega20 case
drm/amd/powerplay: enable DCEFCLK dpm support
drm/amd/powerplay: fix the incorrect type of pptable
drm/amd/powerplay: update smu11_driver_if_navi10.h
drm/amd/powerplay: enable vcn powergating v2
drm/amd/powerplay: add new interface for vcn powergating
amd/powerplay: fix the issue of uclk dpm
amd/powerplay: enable uclk dpm
amd/powerplay: update the vcn pg
drm/amd/powerplay: enable gfxclk ds,dcefclk ds and fw dstate on navi10
drm/amd/powerplay: enable ac/dc feature on navi10
Kevin Wang (56):
drm/amd/powerplay: move the funciton of conv_profile_to_workload to
asic file
drm/amd/powerplay: move the function of get[set]_power_profile to asic
file
drm/amd/powerplay: move the function of uvd&vce dpm to asic file
drm/amd/powerplay: move the function of read_sensor to asic file
drm/amd/powerplay: move the function of is_dpm_running to asic file
drm/amd/powerplay: add smu11 smu_if_version check for navi10
drm/amd/powerplay: implement smc firmware v2.1 for smu11
drm/amd/powerplay: remove duplicate code from smu hw init
drm/amd/powerplay: optimization feature mask function for asic
drm/amd/powerplay: add allowed feature mask for navi10
drm/amd/powerplay: add function get current clock freq interface for
navi10
drm/amd/powerplay: add helper function to get dpm freq informations
drm/amd/powerplay: add function print_clk_levels for navi10
drm/amd/powerplay: add helper function of smu_get_dpm_freq_range
drm/amd/powerplay: add helper function of smu_set_soft_freq_range
drm/amd/powerplay: add helper function of smu_set_hard_freq_range
drm/amd/powerplay: add function force_clk_levels for navi10
drm/amd/powerplay: add function populate_umd_state_clk for navi10
drm/amd/powerplay: add function get_clock_by_type_with_latency for
navi10
drm/amd/powerplay: add function pre_display_config_changed for navi10
drm/amd/powerplay: add function display_configuration_changed for
navi10
drm/amd/powerplay: add funciton force_dpm_limit for navi10
drm/amd/powerplay: add function unforce_dpm_levels for navi10
drm/amd/powerplay: add function get_gpu_power for navi10
drm/amd/powerplay: add function get_current_activity_percent for
navi10
drm/amd/powerplay: move read sensor of UVD[VCE]_POWER to amdgpu_smu
file
drm/amd/powerplay: add function is_dpm_running for navi10
drm/amd/powerplay: add function set_thermal_fan_table for navi10
drm/amd/powerplay: add function get_fan_speed_percent for navi10
drm/amd/powerplay: remove upload_dpm_level function for vega20
Revert "drm/amdgpu: mask some pm interfaces for navi10 because they
are changed or not workable so far"
drm/amd/powerplay: add function get_workload_type_map for swsmu
drm/amd/powerplay: add funciton get[set]_power_profile_mode for navi10
(v2)
drm/amd/powerplay: add function get_profiling_clk_mask for navi10
drm/amd/powerplay: add function notify_smc_display_config_change for
navi10
drm/amd/powerplay: add function set_watermarks_table function for
navi10
drm/amd/powerplay: add function read_sensor for navi10
drm/amd/powerplay: fix dpm freq unit error (10KHz -> Mhz)
drm/amd/powerplay: simplify the interface of
get_current_activity_percent
drm/amd/powerplay: simplify the interface of get_gpu_power
drm/amd/powerplay: fix amdgpu_pm_info show gpu load error
drm/amd/powerplay: add sclk sysfs interface support for navi10
drm/amd/powerplay: enable uclk dpm default on navi10
drm/amd/powerplay: move power_dpm_force_performance_level to
amdgpu_smu file
drm/amd/powerplay: move function get_metrics_table to vega20_ppt
drm/amd/powerplay: move function thermal_get_temperature to veag20_ppt
drm/amd/powerplay: add thermal ctf support for navi10
drm/amd/powerplay: remove smu mutex lock in smu_hw_init
drm/amd/powerplay: remove smu callback funciton get_mclk(get_sclk)
drm/amd/powerplay: fix deadlock issue for smu_force_performance_level
drm/amd/powerplay: fix clk type name error OD_SCLK OD_MCLK
drm/amd/powerplay: move od8_setting helper function to vega20_ppt
drm/amd/powerplay: move od_default_setting callback to asic file
drm/amd/powerplay: simplified od_settings for each asic
drm/amd/powerplay: use pp_feature_mask to control uclk(mclk) dpm
enabled
drm/amd/powerplay: remove unsupport function set_thermal_fan_table for
navi10
Le.Ma (3):
drm/amdgpu: add structures for buffer allocate/release for rlc
autoload
drm/amdgpu: add fw load type flag for rlc autoload
drm/amdgpu: enable virtual display feature for navi10
Leo (Hanghong) Ma (1):
drm/amd/display: Expose send immediate sdp message interface
Leo Li (5):
drm/amdgpu: Split gpu_info_soc_bounding_box out from amdgpu_ucode.h
drm/amd/display: Disconnect DCN2 mpcc when changing tg
drm/amd/display: Clean up locking in dcn*_apply_ctx_for_surface()
drm/amd/display: Guard DML_FAIL_DSC_VALIDATION_FAILURE
drm/amd/display: Properly guard display_mode_vba with DCN2
Leo Liu (16):
drm/amdgpu: add nbio callbacks for vcn doorbell support
drm/amdgpu: add Navi10 VCN firmware support
drm/amdgpu: add VCN2.0 decode ring test
drm/amdgpu: add VCN2.0 decode ib test
drm/amdgpu: add JPEG2.0 decode ring test
drm/amdgpu: add JPEG2.0 decode ring ib test
drm/amdgpu: add initial VCN2.0 support (v2)
drm/amdgpu/VCN2.0: remove powergating for UVDW tile
drm/amdgpu/VCN2.0 remove unused Macro and declaration
drm/amdgpu/VCN2.0: add direct SRAM read and write
drm/amdgpu/VCN2.0: add DPG mode start and stop (v2)
drm/amdgpu/VCN2.0: add DPG pause mode
drm/amdgpu: enable VCN2.0 DPG mode
drm/amdgpu/VCN: add buffer for indirect SRAM usage
drm/amdgpu/VCN: implement indirect DPG SRAM mode
drm/amdgpu/VCN: enable indirect DPG SRAM mode
Marek Olšák (1):
drm/amdgpu: fix PA_SC_FIFO_SIZE for Navi10
Martin Leung (1):
drm/amd/display: removing MODULO change for dcn2
Nicholas Kazlauskas (2):
drm/amd/display: Copy stream updates onto streams
drm/amd/display: Rework CRTC color management
Nikola Cornij (13):
drm/amd/display: Calculate link bandwidth in a common function
drm/amd/display: Remove additional FEC link bandwidth reduction
drm/amd/display: Use 1/8th DSC target bitrate precision for N4:2:2 and
4:2:0 formats
drm/amd/display: Make sure DSC slice height is divisible by 2 for
4:2:0 color format
drm/amd/display: Mark DSC resource as unused after copying to the
secondary ODM pipe
drm/amd/display: Acquire DSC HW resource only if required by stream
drm/amd/display: Consider DSC target bpp precision when calculating
DSC target bpp
drm/amd/display: Make sure line size is not zero in DCN2 line buffer
size calculations
drm/amd/display: Add 170Mpix/sec DSC throughput support
drm/amd/display: Do a reg update instead of set when writing ODM color
format
drm/amd/display: Add support for extended DSC DPCD caps
drm/amd/display: Disable DSC power gating in Diags
drm/amd/display: Enable DSC power-gating for DSC streams
Oak Zeng (3):
drm/amdkfd: Added cwsr trap handler for gfx10
drm/amdkfd: Moved gfx10 cwsr binary to cwsr_trap_handler.h
drm/amdkfd: Parameterize queue_preemption_timeout_ms
Paul Hsieh (1):
drm/amd/display: disable PSR/ABM before destroy DMCU struct
Philip Cox (1):
drm/amdkfd: Add navi10 support to amdkfd. (v2)
Rex Zhu (4):
drm/amdgpu: Add struct kiq_pm4_funcs into kiq struct
drm/amdgpu: Add common gfx func Disable kcq via kiq
drm/amdgpu: Add helper function amdgpu_ring_set_preempt_cond_exec
drm/amdgpu: Add new ring interface preempt_ib
Samson Tam (1):
drm/amd/display: block passive dongle EDID Emulation for USB-C ports
Su Sung Chung (1):
drm/amd/display: make clk_mgr call enable_pme_wa
Tao Zhou (5):
drm/amdgpu: Add psp 11.0 support for navi10.
drm/amd/powerplay/smu11: enable ds socclk by default
drm/amd/powerplay/smu11: add secure board check function (v2)
drm/amd/powerplay/smu11: disable some pp features on navi10 A0 secure
board
drm/amdgpu: correct reference clock value on navi10
Thomas Lim (2):
drm/amd/display: Add power down display on boot flag
drm/amd/display: Add Underflow Asserts to dc
Tony Cheng (1):
drm/amd/display: move dsc clock from plane_resource to stream_resource
Tyler DiBattista (2):
drm/amd/display: Change Min fclk to 1.2Ghz
drm/amd/display: move DWB structs and enums to dc_hw_types
Vitaly Prosyak (5):
drm/amd/display: Add a flags union for 3dlut transformation matrix
drm/amd/display: Add some tm3dlut flags
drm/amd/display: Add 3dlut control flags
drm/amd/display: add flags for gamut map library
drm/amd/display: Integrate color transform3x4 with 3dlut tm
Wenjing Liu (10):
drm/amd/display: remove legacy DSC functions
drm/amd/display: remove target_dpp hack for dsc
drm/amd/display: isolate global double buffer lock programming
drm/amd/display: add global master update lock for DCN2
drm/amd/display: Implement DSC MST fair share algorithm
drm/amd/display: fix a potential issue in DSC logic
drm/amd/display: add dsc_passthrough_support bit in dpcd struct
drm/amd/display: decouple dsc adjustment out of enablement
drm/amd/display: update DSC MST DP virtual DPCD peer device
enumeration policy
drm/amd/display: update dsc max_target_bpp to 16 bpp
Wesley Chalmers (3):
drm/amd/display: DCN2 Engine-specifc encoder allocation
drm/amd/display: Use DCN2 functions instead of DCE
drm/amd/display: Use macro for invalid OPP ID
Xiaojie Yuan (15):
drm/amdgpu/discovery: add ip discovery initial support
drm/amdgpu/discovery: fix calculations of some gfx info
drm/amdgpu/discovery: update definitions of table_info and
binary_header
drm/amdgpu/discovery: add harvest info data table
drm/amdgpu/discovery: use hardcoded mmRCC_CONFIG_MEMSIZE
drm/amdgpu/discovery: fix hwid for nbio
drm/amdgpu/discovery: stop taking psp header into account
drm/amdgpu/discovery: update definition for struct die_header
drm/amdgpu/discovery: stop converting the units of base addresses
drm/amdgpu/discovery: add module param for ip discovery enablement
drm/amdgpu/discovery: refactor ip list traversal
drm/amdgpu/gfx10: fix resume failure when enabling async gfx ring
drm/amdgpu/gfx10: drop redundant se/sh selection
drm/amdgpu/gfx10: fix unbalanced MAP/UNMAP_QUEUES when async_gfx_ring
is disabled
drm/amd/display: use fixed-width data type for soc bounding box struct
Yongqiang Sun (5):
drm/amd/display: DCN2 reg refactors
drm/amd/display: Remove REFCYC regs
drm/amd/display: Remove duplicate define of TO_DCN20_HUBBUB
drm/amd/display: Refactor program watermark.
drm/amd/display: DCHUB requestors numbers for Navi.
hersen wu (17):
drm/amd/powerplay: allow dc request uclk change
drm/amd/powerplay: notify smu with active display count
drm/amd/powerplay: wake up azalia from d3 by sending smu message
drm/amd/powerplay: add interface to get uclk dpm table
drm/amd/powerplay: allow dc request uclk change
drm/amd/powerplay: notify smu with active display count
drm/amd/powrplay: add interface for dc to get max clock values
drm/amd/powerplay: add interface to get uclk dpm table
drm/amd/display: hook navi10 pplib functions
drm/amd/display/dc: fix azalia workaround sw implementation bug
drm/amd/display: disable dcn20 abm feature for bring up
drm/amd/display: do not need otg lock if otg is not active
drm/amd/display: skip dsc config for navi10 bring up
drm/amd/display: navi10 bring up skip dsc encoder config
drm/amd/display: Add vupdate interrupt sources to NV10
drm/amd/display: Disable display writeback on Linux for NV10
drm/amd/display/dc: set num-dwb = 1 as navi10 asic cap
tiancyin (7):
drm/amdgpu/gfx10: update gfx golden settings
drm/amdgpu: disable some gfx light sleep
drm/amdgpu/sdma5: fix a sdma potential hang in VK_Examples test
drm/amd/powerplay: disable uclk dpm by default
drm/amdgpu/gfx10: update gfx golden settings
drm/amd/powerplay: add ppt interface version log
drm/amdgpu: add new navi10 DIDs
drivers/gpu/drm/amd/amdgpu/Makefile | 30 +-
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 19 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c | 19 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h | 1 +
.../drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c | 975 +
.../gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c | 53 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 5 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_csa.c | 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c | 178 +
drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.h | 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 57 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 415 +
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.h | 34 +
drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell.h | 40 +
drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c | 52 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h | 7 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 44 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c | 18 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 180 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h | 86 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c | 3 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c | 7 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_job.h | 3 +
drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 10 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h | 101 +
drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 52 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 175 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h | 12 +
drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c | 10 +
drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h | 16 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.h | 98 +
drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c | 27 +
drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h | 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_socbb.h | 82 +
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 4 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c | 43 +
drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h | 66 +
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 56 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h | 71 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h | 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 14 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h | 12 +-
drivers/gpu/drm/amd/amdgpu/athub_v2_0.c | 101 +
drivers/gpu/drm/amd/amdgpu/athub_v2_0.h | 30 +
drivers/gpu/drm/amd/amdgpu/clearstate_gfx10.h | 975 +
drivers/gpu/drm/amd/amdgpu/dce_virtual.c | 1 +
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 5218 +
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.h | 29 +
drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c | 4 +-
drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 4 +-
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 26 +-
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 26 +-
drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c | 353 +
drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.h | 35 +
drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 916 +
drivers/gpu/drm/amd/amdgpu/gmc_v10_0.h | 30 +
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 14 +-
drivers/gpu/drm/amd/amdgpu/mes_v10_1.c | 365 +
drivers/gpu/drm/amd/amdgpu/mes_v10_1.h | 29 +
drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c | 444 +
drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.h | 35 +
drivers/gpu/drm/amd/amdgpu/navi10_ih.c | 486 +
drivers/gpu/drm/amd/amdgpu/navi10_ih.h | 29 +
drivers/gpu/drm/amd/amdgpu/navi10_reg_init.c | 68 +
.../gpu/drm/amd/amdgpu/navi10_sdma_pkt_open.h | 4806 +
drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c | 334 +
drivers/gpu/drm/amd/amdgpu/nbio_v2_3.h | 31 +
drivers/gpu/drm/amd/amdgpu/nv.c | 776 +
drivers/gpu/drm/amd/amdgpu/nv.h | 33 +
drivers/gpu/drm/amd/amdgpu/nvd.h | 418 +
drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h | 118 +-
drivers/gpu/drm/amd/amdgpu/psp_v11_0.c | 121 +-
drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c | 1687 +
drivers/gpu/drm/amd/amdgpu/sdma_v5_0.h | 45 +
drivers/gpu/drm/amd/amdgpu/soc15.c | 11 +-
drivers/gpu/drm/amd/amdgpu/soc15.h | 8 +
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 13 +
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c | 2261 +
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.h | 29 +
drivers/gpu/drm/amd/amdkfd/Makefile | 3 +
.../gpu/drm/amd/amdkfd/cwsr_trap_handler.h | 299 +
.../amd/amdkfd/cwsr_trap_handler_gfx10.asm | 1124 +
drivers/gpu/drm/amd/amdkfd/kfd_crat.c | 5 +
drivers/gpu/drm/amd/amdkfd/kfd_device.c | 31 +-
.../drm/amd/amdkfd/kfd_device_queue_manager.c | 28 +-
.../drm/amd/amdkfd/kfd_device_queue_manager.h | 4 +-
.../amd/amdkfd/kfd_device_queue_manager_v10.c | 87 +
drivers/gpu/drm/amd/amdkfd/kfd_flat_memory.c | 1 +
drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c | 3 +
drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.h | 1 +
.../gpu/drm/amd/amdkfd/kfd_kernel_queue_v10.c | 348 +
.../gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c | 498 +
.../gpu/drm/amd/amdkfd/kfd_packet_manager.c | 3 +
drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 18 +-
drivers/gpu/drm/amd/amdkfd/kfd_process.c | 1 +
drivers/gpu/drm/amd/amdkfd/kfd_topology.c | 1 +
drivers/gpu/drm/amd/display/Kconfig | 19 +
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 77 +-
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 17 +-
.../amd/display/amdgpu_dm/amdgpu_dm_color.c | 473 +-
.../amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 10 +
.../amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c | 298 +-
drivers/gpu/drm/amd/display/dc/Makefile | 16 +-
.../drm/amd/display/dc/bios/bios_parser2.c | 4 +
.../display/dc/bios/command_table_helper2.c | 6 +
.../gpu/drm/amd/display/dc/calcs/dcn_calcs.c | 18 +-
.../gpu/drm/amd/display/dc/clk_mgr/Makefile | 12 +
.../gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c | 7 +
.../display/dc/clk_mgr/dce100/dce_clk_mgr.h | 22 -
.../display/dc/clk_mgr/dcn10/rv1_clk_mgr.c | 14 +
.../display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c | 391 +
.../display/dc/clk_mgr/dcn20/dcn20_clk_mgr.h | 48 +
drivers/gpu/drm/amd/display/dc/core/dc.c | 244 +-
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 77 +
.../gpu/drm/amd/display/dc/core/dc_link_dp.c | 150 +
.../drm/amd/display/dc/core/dc_link_hwss.c | 144 +
.../gpu/drm/amd/display/dc/core/dc_resource.c | 15 +
.../gpu/drm/amd/display/dc/core/dc_stream.c | 197 +
.../gpu/drm/amd/display/dc/core/dc_surface.c | 73 +
.../drm/amd/display/dc/core/dc_vm_helper.c | 93 +-
drivers/gpu/drm/amd/display/dc/dc.h | 136 +
drivers/gpu/drm/amd/display/dc/dc_dp_types.h | 127 +
drivers/gpu/drm/amd/display/dc/dc_dsc.h | 62 +
drivers/gpu/drm/amd/display/dc/dc_hw_types.h | 117 +-
drivers/gpu/drm/amd/display/dc/dc_link.h | 10 +
drivers/gpu/drm/amd/display/dc/dc_stream.h | 74 +-
drivers/gpu/drm/amd/display/dc/dc_types.h | 116 +
drivers/gpu/drm/amd/display/dc/dce/dce_abm.h | 20 +
drivers/gpu/drm/amd/display/dc/dce/dce_aux.h | 10 +
.../drm/amd/display/dc/dce/dce_clock_source.c | 80 +
.../drm/amd/display/dc/dce/dce_clock_source.h | 42 +
drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c | 88 +
drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h | 8 +
.../gpu/drm/amd/display/dc/dce/dce_hwseq.h | 127 +
.../gpu/drm/amd/display/dc/dce/dce_i2c_hw.c | 34 +
.../gpu/drm/amd/display/dc/dce/dce_i2c_hw.h | 22 +
.../display/dc/dce110/dce110_hw_sequencer.c | 63 +-
.../gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c | 10 +
.../gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h | 5 +
.../drm/amd/display/dc/dcn10/dcn10_dpp_cm.c | 4 +
.../drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c | 8 +
.../gpu/drm/amd/display/dc/dcn10/dcn10_dwb.c | 136 +
.../gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h | 271 +
.../drm/amd/display/dc/dcn10/dcn10_hubbub.c | 45 +-
.../gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c | 34 +-
.../gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h | 8 +
.../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 109 +-
.../amd/display/dc/dcn10/dcn10_hw_sequencer.h | 2 +
.../gpu/drm/amd/display/dc/dcn10/dcn10_ipp.c | 24 +
.../gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h | 43 +
.../amd/display/dc/dcn10/dcn10_link_encoder.h | 174 +
.../gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c | 6 +
.../gpu/drm/amd/display/dc/dcn10/dcn10_opp.c | 8 +
.../gpu/drm/amd/display/dc/dcn10/dcn10_optc.c | 29 +-
.../gpu/drm/amd/display/dc/dcn10/dcn10_optc.h | 34 +-
.../drm/amd/display/dc/dcn10/dcn10_resource.c | 4 +-
.../display/dc/dcn10/dcn10_stream_encoder.h | 40 +
drivers/gpu/drm/amd/display/dc/dcn20/Makefile | 17 +
.../gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c | 157 +
.../gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h | 116 +
.../gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c | 502 +
.../gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h | 698 +
.../drm/amd/display/dc/dcn20/dcn20_dpp_cm.c | 990 +
.../gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c | 694 +
.../gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h | 575 +
.../gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c | 332 +
.../gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h | 458 +
.../drm/amd/display/dc/dcn20/dcn20_dwb_scl.c | 877 +
.../drm/amd/display/dc/dcn20/dcn20_hubbub.c | 592 +
.../drm/amd/display/dc/dcn20/dcn20_hubbub.h | 107 +
.../gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c | 700 +
.../gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h | 277 +
.../drm/amd/display/dc/dcn20/dcn20_hwseq.c | 2007 +
.../drm/amd/display/dc/dcn20/dcn20_hwseq.h | 103 +
.../amd/display/dc/dcn20/dcn20_link_encoder.c | 460 +
.../amd/display/dc/dcn20/dcn20_link_encoder.h | 173 +
.../drm/amd/display/dc/dcn20/dcn20_mmhubbub.c | 323 +
.../drm/amd/display/dc/dcn20/dcn20_mmhubbub.h | 544 +
.../gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c | 526 +
.../gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h | 285 +
.../gpu/drm/amd/display/dc/dcn20/dcn20_opp.c | 355 +
.../gpu/drm/amd/display/dc/dcn20/dcn20_opp.h | 158 +
.../gpu/drm/amd/display/dc/dcn20/dcn20_optc.c | 542 +
.../gpu/drm/amd/display/dc/dcn20/dcn20_optc.h | 116 +
.../drm/amd/display/dc/dcn20/dcn20_resource.c | 3175 +
.../drm/amd/display/dc/dcn20/dcn20_resource.h | 133 +
.../display/dc/dcn20/dcn20_stream_encoder.c | 608 +
.../display/dc/dcn20/dcn20_stream_encoder.h | 107 +
.../gpu/drm/amd/display/dc/dcn20/dcn20_vmid.c | 59 +
.../gpu/drm/amd/display/dc/dcn20/dcn20_vmid.h | 90 +
drivers/gpu/drm/amd/display/dc/dm_helpers.h | 7 +
drivers/gpu/drm/amd/display/dc/dm_pp_smu.h | 113 +-
drivers/gpu/drm/amd/display/dc/dml/Makefile | 14 +-
.../dc/dml/dcn20/display_mode_vba_20.c | 5104 +
.../dc/dml/dcn20/display_mode_vba_20.h | 32 +
.../dc/dml/dcn20/display_rq_dlg_calc_20.c | 1701 +
.../dc/dml/dcn20/display_rq_dlg_calc_20.h | 74 +
.../amd/display/dc/dml/display_mode_enums.h | 6 +-
.../drm/amd/display/dc/dml/display_mode_lib.c | 22 +
.../drm/amd/display/dc/dml/display_mode_lib.h | 36 +-
.../amd/display/dc/dml/display_mode_structs.h | 27 +
.../drm/amd/display/dc/dml/display_mode_vba.c | 839 +
.../drm/amd/display/dc/dml/display_mode_vba.h | 854 +
drivers/gpu/drm/amd/display/dc/dsc/Makefile | 13 +
drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c | 858 +
.../gpu/drm/amd/display/dc/dsc/drm_dsc_dc.c | 382 +
.../gpu/drm/amd/display/dc/dsc/dscc_types.h | 54 +
.../gpu/drm/amd/display/dc/dsc/qp_tables.h | 706 +
drivers/gpu/drm/amd/display/dc/dsc/rc_calc.c | 258 +
drivers/gpu/drm/amd/display/dc/dsc/rc_calc.h | 85 +
.../gpu/drm/amd/display/dc/dsc/rc_calc_dpi.c | 147 +
drivers/gpu/drm/amd/display/dc/gpio/Makefile | 11 +
.../display/dc/gpio/dcn20/hw_factory_dcn20.c | 212 +
.../display/dc/gpio/dcn20/hw_factory_dcn20.h | 33 +
.../dc/gpio/dcn20/hw_translate_dcn20.c | 382 +
.../dc/gpio/dcn20/hw_translate_dcn20.h | 35 +
.../gpu/drm/amd/display/dc/gpio/ddc_regs.h | 53 +
drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c | 15 +
.../gpu/drm/amd/display/dc/gpio/hw_factory.c | 9 +
.../drm/amd/display/dc/gpio/hw_translate.c | 9 +
.../gpu/drm/amd/display/dc/inc/core_status.h | 5 +
.../gpu/drm/amd/display/dc/inc/core_types.h | 66 +
.../gpu/drm/amd/display/dc/inc/dc_link_dp.h | 7 +
.../amd/display/dc/inc/hw/clk_mgr_internal.h | 88 +-
.../gpu/drm/amd/display/dc/inc/hw/dchubbub.h | 58 +
drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h | 53 +
drivers/gpu/drm/amd/display/dc/inc/hw/dsc.h | 101 +
drivers/gpu/drm/amd/display/dc/inc/hw/dwb.h | 180 +
drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h | 30 +-
.../gpu/drm/amd/display/dc/inc/hw/hw_shared.h | 50 +-
.../drm/amd/display/dc/inc/hw/link_encoder.h | 27 +
.../gpu/drm/amd/display/dc/inc/hw/mcif_wb.h | 105 +
drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h | 52 +
drivers/gpu/drm/amd/display/dc/inc/hw/opp.h | 29 +
.../amd/display/dc/inc/hw/stream_encoder.h | 46 +
.../amd/display/dc/inc/hw/timing_generator.h | 32 +
drivers/gpu/drm/amd/display/dc/inc/hw/vmid.h | 1 +
.../gpu/drm/amd/display/dc/inc/hw_sequencer.h | 53 +
drivers/gpu/drm/amd/display/dc/inc/resource.h | 6 +
.../gpu/drm/amd/display/dc/inc/vm_helper.h | 16 +-
drivers/gpu/drm/amd/display/dc/irq/Makefile | 10 +
.../display/dc/irq/dcn10/irq_service_dcn10.c | 2 +-
.../display/dc/irq/dcn20/irq_service_dcn20.c | 373 +
.../display/dc/irq/dcn20/irq_service_dcn20.h | 34 +
.../dc/virtual/virtual_stream_encoder.c | 15 +
.../gpu/drm/amd/display/include/dal_asic_id.h | 25 +
.../gpu/drm/amd/display/include/dal_types.h | 3 +
.../drm/amd/display/include/logger_types.h | 10 +
.../drm/amd/display/modules/inc/mod_shared.h | 60 +
.../drm/amd/display/modules/inc/mod_vmid.h | 46 +
.../gpu/drm/amd/display/modules/vmid/vmid.c | 167 +
drivers/gpu/drm/amd/include/amd_shared.h | 8 +-
.../asic_reg/athub/athub_2_0_0_default.h | 272 +
.../asic_reg/athub/athub_2_0_0_offset.h | 514 +
.../asic_reg/athub/athub_2_0_0_sh_mask.h | 2264 +
.../include/asic_reg/clk/clk_11_0_0_offset.h | 33 +
.../include/asic_reg/clk/clk_11_0_0_sh_mask.h | 38 +
.../include/asic_reg/dcn/dcn_2_0_0_offset.h | 17535 +++
.../include/asic_reg/dcn/dcn_2_0_0_sh_mask.h | 68024 ++++++++
.../include/asic_reg/gc/gc_10_1_0_default.h | 6028 +
.../include/asic_reg/gc/gc_10_1_0_offset.h | 11339 ++
.../include/asic_reg/gc/gc_10_1_0_sh_mask.h | 43963 ++++++
.../include/asic_reg/hdp/hdp_5_0_0_offset.h | 217 +
.../include/asic_reg/hdp/hdp_5_0_0_sh_mask.h | 659 +
.../asic_reg/mmhub/mmhub_2_0_0_default.h | 927 +
.../asic_reg/mmhub/mmhub_2_0_0_offset.h | 1799 +
.../asic_reg/mmhub/mmhub_2_0_0_sh_mask.h | 7567 +
.../amd/include/asic_reg/mp/mp_11_0_sh_mask.h | 429 +
.../include/asic_reg/nbio/nbio_2_3_default.h | 18521 +++
.../include/asic_reg/nbio/nbio_2_3_offset.h | 14663 ++
.../include/asic_reg/nbio/nbio_2_3_sh_mask.h | 120339 +++++++++++++++
.../asic_reg/oss/osssys_5_0_0_offset.h | 353 +
.../asic_reg/oss/osssys_5_0_0_sh_mask.h | 1305 +
.../asic_reg/smuio/smuio_11_0_0_offset.h | 323 +
.../asic_reg/smuio/smuio_11_0_0_sh_mask.h | 689 +
.../include/asic_reg/vcn/vcn_2_0_0_offset.h | 1008 +
.../include/asic_reg/vcn/vcn_2_0_0_sh_mask.h | 3815 +
drivers/gpu/drm/amd/include/atomfirmware.h | 188 +-
drivers/gpu/drm/amd/include/discovery.h | 165 +
.../ivsrcid/{ => dcn}/irqsrcs_dcn_1_0.h | 0
.../include/ivsrcid/gfx/irqsrcs_gfx_10_1.h | 53 +
.../include/ivsrcid/sdma0/irqsrcs_sdma0_5_0.h | 43 +
.../include/ivsrcid/sdma1/irqsrcs_sdma1_5_0.h | 44 +
.../amd/include/ivsrcid/vcn/irqsrcs_vcn_2_0.h | 32 +
drivers/gpu/drm/amd/include/navi10_enum.h | 22764 +++
.../gpu/drm/amd/include/navi10_ip_offset.h | 855 +
drivers/gpu/drm/amd/include/soc15_hw_ip.h | 4 +-
drivers/gpu/drm/amd/include/v10_structs.h | 1258 +
drivers/gpu/drm/amd/powerplay/Makefile | 2 +-
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 328 +-
.../gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 329 +-
.../powerplay/inc/smu11_driver_if_navi10.h | 1069 +
drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h | 18 +
.../drm/amd/powerplay/inc/smu_v11_0_ppsmc.h | 39 +-
.../drm/amd/powerplay/inc/smu_v11_0_pptable.h | 2 +-
drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 1316 +
drivers/gpu/drm/amd/powerplay/navi10_ppt.h | 28 +
drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 1142 +-
drivers/gpu/drm/amd/powerplay/vega20_ppt.c | 1129 +-
drivers/gpu/drm/amd/powerplay/vega20_ppt.h | 6 +
include/drm/amd_asic_type.h | 1 +
include/drm/drm_dp_helper.h | 9 +
include/uapi/drm/amdgpu_drm.h | 4 +
304 files changed, 412412 insertions(+), 1745 deletions(-)
create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.h
create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h
create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_socbb.h
create mode 100644 drivers/gpu/drm/amd/amdgpu/athub_v2_0.c
create mode 100644 drivers/gpu/drm/amd/amdgpu/athub_v2_0.h
create mode 100644 drivers/gpu/drm/amd/amdgpu/clearstate_gfx10.h
create mode 100644 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
create mode 100644 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.h
create mode 100644 drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c
create mode 100644 drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.h
create mode 100644 drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
create mode 100644 drivers/gpu/drm/amd/amdgpu/gmc_v10_0.h
create mode 100644 drivers/gpu/drm/amd/amdgpu/mes_v10_1.c
create mode 100644 drivers/gpu/drm/amd/amdgpu/mes_v10_1.h
create mode 100644 drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c
create mode 100644 drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.h
create mode 100644 drivers/gpu/drm/amd/amdgpu/navi10_ih.c
create mode 100644 drivers/gpu/drm/amd/amdgpu/navi10_ih.h
create mode 100644 drivers/gpu/drm/amd/amdgpu/navi10_reg_init.c
create mode 100644 drivers/gpu/drm/amd/amdgpu/navi10_sdma_pkt_open.h
create mode 100644 drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c
create mode 100644 drivers/gpu/drm/amd/amdgpu/nbio_v2_3.h
create mode 100644 drivers/gpu/drm/amd/amdgpu/nv.c
create mode 100644 drivers/gpu/drm/amd/amdgpu/nv.h
create mode 100644 drivers/gpu/drm/amd/amdgpu/nvd.h
create mode 100644 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
create mode 100644 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.h
create mode 100644 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
create mode 100644 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.h
create mode 100644 drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx10.asm
create mode 100644 drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_v10.c
create mode 100644 drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_v10.c
create mode 100644 drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c
create mode 100644 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
create mode 100644 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.h
create mode 100644 drivers/gpu/drm/amd/display/dc/dc_dsc.h
create mode 100644 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.c
create mode 100644 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h
create mode 100644 drivers/gpu/drm/amd/display/dc/dcn20/Makefile
create mode 100644 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c
create mode 100644 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h
create mode 100644 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c
create mode 100644 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h
create mode 100644 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c
create mode 100644 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c
create mode 100644 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h
create mode 100644 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c
create mode 100644 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h
create mode 100644 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb_scl.c
create mode 100644 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c
create mode 100644 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.h
create mode 100644 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c
create mode 100644 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h
create mode 100644 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
create mode 100644 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.h
create mode 100644 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.c
create mode 100644 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.h
create mode 100644 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.c
create mode 100644 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h
create mode 100644 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c
create mode 100644 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h
create mode 100644 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.c
create mode 100644 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.h
create mode 100644 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c
create mode 100644 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h
create mode 100644 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
create mode 100644 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h
create mode 100644 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c
create mode 100644 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.h
create mode 100644 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_vmid.c
create mode 100644 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_vmid.h
create mode 100644 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
create mode 100644 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.h
create mode 100644 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c
create mode 100644 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.h
create mode 100644 drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
create mode 100644 drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
create mode 100644 drivers/gpu/drm/amd/display/dc/dsc/Makefile
create mode 100644 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
create mode 100644 drivers/gpu/drm/amd/display/dc/dsc/drm_dsc_dc.c
create mode 100644 drivers/gpu/drm/amd/display/dc/dsc/dscc_types.h
create mode 100644 drivers/gpu/drm/amd/display/dc/dsc/qp_tables.h
create mode 100644 drivers/gpu/drm/amd/display/dc/dsc/rc_calc.c
create mode 100644 drivers/gpu/drm/amd/display/dc/dsc/rc_calc.h
create mode 100644 drivers/gpu/drm/amd/display/dc/dsc/rc_calc_dpi.c
create mode 100644 drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_factory_dcn20.c
create mode 100644 drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_factory_dcn20.h
create mode 100644 drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c
create mode 100644 drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.h
create mode 100644 drivers/gpu/drm/amd/display/dc/inc/hw/dsc.h
create mode 100644 drivers/gpu/drm/amd/display/dc/inc/hw/dwb.h
create mode 100644 drivers/gpu/drm/amd/display/dc/inc/hw/mcif_wb.h
create mode 100644 drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c
create mode 100644 drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.h
create mode 100644 drivers/gpu/drm/amd/display/modules/inc/mod_vmid.h
create mode 100644 drivers/gpu/drm/amd/display/modules/vmid/vmid.c
create mode 100644 drivers/gpu/drm/amd/include/asic_reg/athub/athub_2_0_0_default.h
create mode 100644 drivers/gpu/drm/amd/include/asic_reg/athub/athub_2_0_0_offset.h
create mode 100644 drivers/gpu/drm/amd/include/asic_reg/athub/athub_2_0_0_sh_mask.h
create mode 100644 drivers/gpu/drm/amd/include/asic_reg/clk/clk_11_0_0_offset.h
create mode 100644 drivers/gpu/drm/amd/include/asic_reg/clk/clk_11_0_0_sh_mask.h
create mode 100644 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h
create mode 100644 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_sh_mask.h
create mode 100644 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_default.h
create mode 100644 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h
create mode 100644 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h
create mode 100644 drivers/gpu/drm/amd/include/asic_reg/hdp/hdp_5_0_0_offset.h
create mode 100644 drivers/gpu/drm/amd/include/asic_reg/hdp/hdp_5_0_0_sh_mask.h
create mode 100644 drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_2_0_0_default.h
create mode 100644 drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_2_0_0_offset.h
create mode 100644 drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_2_0_0_sh_mask.h
create mode 100644 drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_2_3_default.h
create mode 100644 drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_2_3_offset.h
create mode 100644 drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_2_3_sh_mask.h
create mode 100644 drivers/gpu/drm/amd/include/asic_reg/oss/osssys_5_0_0_offset.h
create mode 100644 drivers/gpu/drm/amd/include/asic_reg/oss/osssys_5_0_0_sh_mask.h
create mode 100644 drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_11_0_0_offset.h
create mode 100644 drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_11_0_0_sh_mask.h
create mode 100644 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_offset.h
create mode 100644 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h
create mode 100644 drivers/gpu/drm/amd/include/discovery.h
rename drivers/gpu/drm/amd/include/ivsrcid/{ => dcn}/irqsrcs_dcn_1_0.h (100%)
create mode 100644 drivers/gpu/drm/amd/include/ivsrcid/gfx/irqsrcs_gfx_10_1.h
create mode 100644 drivers/gpu/drm/amd/include/ivsrcid/sdma0/irqsrcs_sdma0_5_0.h
create mode 100644 drivers/gpu/drm/amd/include/ivsrcid/sdma1/irqsrcs_sdma1_5_0.h
create mode 100644 drivers/gpu/drm/amd/include/ivsrcid/vcn/irqsrcs_vcn_2_0.h
create mode 100644 drivers/gpu/drm/amd/include/navi10_enum.h
create mode 100644 drivers/gpu/drm/amd/include/navi10_ip_offset.h
create mode 100644 drivers/gpu/drm/amd/include/v10_structs.h
create mode 100644 drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_navi10.h
create mode 100644 drivers/gpu/drm/amd/powerplay/navi10_ppt.c
create mode 100644 drivers/gpu/drm/amd/powerplay/navi10_ppt.h
--
2.20.1
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