[PATCH 330/459] drm/amd/display: Add DCN2 DWB
Alex Deucher
alexdeucher at gmail.com
Mon Jun 17 19:44:31 UTC 2019
From: Harry Wentland <harry.wentland at amd.com>
Add support to program the DCN2 DWB (Display Writeback)
HW Blocks:
+--------++------+ +----------+
| HUBBUB || HUBP | <-- | MMHUBBUB |
+--------++------+ +----------+
| ^
v |
+--------+ +--------+
| DPP | | DWB |
+--------+ +--------+
|
v ^
+--------+ |
| MPC | |
+--------+ |
| |
v |
+-------+ |
| OPP | |
+-------+ |
| |
v |
+--------+ /
| OPTC | --------------
+--------+
|
v
+--------+ +--------+
| DIO | | DCCG |
+--------+ +--------+
Signed-off-by: Harry Wentland <harry.wentland at amd.com>
Signed-off-by: Alex Deucher <alexander.deucher at amd.com>
---
drivers/gpu/drm/amd/display/dc/dc_types.h | 26 +
.../gpu/drm/amd/display/dc/dcn10/dcn10_dwb.c | 136 +++
.../gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h | 271 ++++++
.../gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c | 315 +++++++
.../gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h | 458 +++++++++
.../drm/amd/display/dc/dcn20/dcn20_dwb_scl.c | 877 ++++++++++++++++++
.../gpu/drm/amd/display/dc/inc/core_types.h | 52 ++
drivers/gpu/drm/amd/display/dc/inc/hw/dwb.h | 187 ++++
.../gpu/drm/amd/display/dc/inc/hw/mcif_wb.h | 105 +++
9 files changed, 2427 insertions(+)
create mode 100644 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.c
create mode 100644 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h
create mode 100644 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c
create mode 100644 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h
create mode 100644 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb_scl.c
create mode 100644 drivers/gpu/drm/amd/display/dc/inc/hw/dwb.h
create mode 100644 drivers/gpu/drm/amd/display/dc/inc/hw/mcif_wb.h
diff --git a/drivers/gpu/drm/amd/display/dc/dc_types.h b/drivers/gpu/drm/amd/display/dc/dc_types.h
index 92a670894c05..01793aa3e093 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_types.h
@@ -421,6 +421,32 @@ enum display_content_type {
DISPLAY_CONTENT_TYPE_GAME = 8
};
+#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+/* writeback */
+struct dc_dwb_cnv_params {
+ unsigned int src_width; /* input active width */
+ unsigned int src_height; /* input active height (half-active height in interlaced mode) */
+ unsigned int crop_width; /* cropped window width at cnv output */
+ bool crop_en; /* window cropping enable in cnv */
+ unsigned int crop_height; /* cropped window height at cnv output */
+ unsigned int crop_x; /* cropped window start x value at cnv output */
+ unsigned int crop_y; /* cropped window start y value at cnv output */
+ enum dwb_cnv_out_bpc cnv_out_bpc; /* cnv output pixel depth - 8bpc or 10bpc */
+};
+
+struct dc_dwb_params {
+ struct dc_dwb_cnv_params cnv_params; /* CNV source size and cropping window parameters */
+ unsigned int dest_width; /* Destination width */
+ unsigned int dest_height; /* Destination height */
+ enum dwb_scaler_mode out_format; /* default = YUV420 - TODO: limit this to 0 and 1 on dcn3 */
+ enum dwb_output_depth output_depth; /* output pixel depth - 8bpc or 10bpc */
+ enum dwb_capture_rate capture_rate; /* controls the frame capture rate */
+ struct scaling_taps scaler_taps; /* Scaling taps */
+ enum dwb_subsample_position subsample_position;
+ struct dc_transfer_func *out_transfer_func;
+};
+#endif
+
/* audio*/
union audio_sample_rates {
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.c
new file mode 100644
index 000000000000..374cc9acda3b
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.c
@@ -0,0 +1,136 @@
+/*
+ * Copyright 2012-17 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
+
+#include "reg_helper.h"
+#include "resource.h"
+#include "dwb.h"
+#include "dcn10_dwb.h"
+
+
+#define REG(reg)\
+ dwbc10->dwbc_regs->reg
+
+#define CTX \
+ dwbc10->base.ctx
+
+#undef FN
+#define FN(reg_name, field_name) \
+ dwbc10->dwbc_shift->field_name, dwbc10->dwbc_mask->field_name
+
+#define TO_DCN10_DWBC(dwbc_base) \
+ container_of(dwbc_base, struct dcn10_dwbc, base)
+
+static bool dwb1_get_caps(struct dwbc *dwbc, struct dwb_caps *caps)
+{
+ if (caps) {
+ caps->adapter_id = 0; /* we only support 1 adapter currently */
+ caps->hw_version = DCN_VERSION_1_0;
+ caps->num_pipes = 2;
+ memset(&caps->reserved, 0, sizeof(caps->reserved));
+ memset(&caps->reserved2, 0, sizeof(caps->reserved2));
+ caps->sw_version = dwb_ver_1_0;
+ caps->caps.support_dwb = true;
+ caps->caps.support_ogam = false;
+ caps->caps.support_wbscl = true;
+ caps->caps.support_ocsc = false;
+ return true;
+ } else {
+ return false;
+ }
+}
+
+static bool dwb1_enable(struct dwbc *dwbc, struct dc_dwb_params *params)
+{
+ struct dcn10_dwbc *dwbc10 = TO_DCN10_DWBC(dwbc);
+
+ /* disable first. */
+ dwbc->funcs->disable(dwbc);
+
+ /* disable power gating */
+ REG_UPDATE_5(WB_EC_CONFIG, DISPCLK_R_WB_GATE_DIS, 1,
+ DISPCLK_G_WB_GATE_DIS, 1, DISPCLK_G_WBSCL_GATE_DIS, 1,
+ WB_LB_LS_DIS, 1, WB_LUT_LS_DIS, 1);
+
+ REG_UPDATE(WB_ENABLE, WB_ENABLE, 1);
+
+ return true;
+}
+
+static bool dwb1_disable(struct dwbc *dwbc)
+{
+ struct dcn10_dwbc *dwbc10 = TO_DCN10_DWBC(dwbc);
+
+ /* disable CNV */
+ REG_UPDATE(CNV_MODE, CNV_FRAME_CAPTURE_EN, 0);
+
+ /* disable WB */
+ REG_UPDATE(WB_ENABLE, WB_ENABLE, 0);
+
+ /* soft reset */
+ REG_UPDATE(WB_SOFT_RESET, WB_SOFT_RESET, 1);
+ REG_UPDATE(WB_SOFT_RESET, WB_SOFT_RESET, 0);
+
+ /* enable power gating */
+ REG_UPDATE_5(WB_EC_CONFIG, DISPCLK_R_WB_GATE_DIS, 0,
+ DISPCLK_G_WB_GATE_DIS, 0, DISPCLK_G_WBSCL_GATE_DIS, 0,
+ WB_LB_LS_DIS, 0, WB_LUT_LS_DIS, 0);
+
+ return true;
+}
+
+const struct dwbc_funcs dcn10_dwbc_funcs = {
+ .get_caps = dwb1_get_caps,
+ .enable = dwb1_enable,
+ .disable = dwb1_disable,
+ .update = NULL,
+ .set_stereo = NULL,
+ .set_new_content = NULL,
+#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ .set_warmup = NULL,
+#endif
+ .dwb_set_scaler = NULL,
+};
+
+void dcn10_dwbc_construct(struct dcn10_dwbc *dwbc10,
+ struct dc_context *ctx,
+ const struct dcn10_dwbc_registers *dwbc_regs,
+ const struct dcn10_dwbc_shift *dwbc_shift,
+ const struct dcn10_dwbc_mask *dwbc_mask,
+ int inst)
+{
+ dwbc10->base.ctx = ctx;
+
+ dwbc10->base.inst = inst;
+ dwbc10->base.funcs = &dcn10_dwbc_funcs;
+
+ dwbc10->dwbc_regs = dwbc_regs;
+ dwbc10->dwbc_shift = dwbc_shift;
+ dwbc10->dwbc_mask = dwbc_mask;
+}
+
+
+#endif
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h
new file mode 100644
index 000000000000..c175edd0bae7
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h
@@ -0,0 +1,271 @@
+/* Copyright 2012-17 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+#ifndef __DC_DWBC_DCN10_H__
+#define __DC_DWBC_DCN10_H__
+
+#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
+
+/* DCN */
+#define BASE_INNER(seg) \
+ DCE_BASE__INST0_SEG ## seg
+
+#define BASE(seg) \
+ BASE_INNER(seg)
+
+#define SR(reg_name)\
+ .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \
+ mm ## reg_name
+
+#define SRI(reg_name, block, id)\
+ .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
+ mm ## block ## id ## _ ## reg_name
+
+
+#define SRII(reg_name, block, id)\
+ .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
+ mm ## block ## id ## _ ## reg_name
+
+#define SF(reg_name, field_name, post_fix)\
+ .field_name = reg_name ## __ ## field_name ## post_fix
+
+
+#define DWBC_COMMON_REG_LIST_DCN1_0(inst) \
+ SRI(WB_ENABLE, CNV, inst),\
+ SRI(WB_EC_CONFIG, CNV, inst),\
+ SRI(CNV_MODE, CNV, inst),\
+ SRI(WB_SOFT_RESET, CNV, inst),\
+ SRI(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB, inst),\
+ SRI(MCIF_WB_BUF_PITCH, MCIF_WB, inst),\
+ SRI(MCIF_WB_ARBITRATION_CONTROL, MCIF_WB, inst),\
+ SRI(MCIF_WB_SCLK_CHANGE, MCIF_WB, inst),\
+ SRI(MCIF_WB_BUF_1_ADDR_Y, MCIF_WB, inst),\
+ SRI(MCIF_WB_BUF_1_ADDR_Y_OFFSET, MCIF_WB, inst),\
+ SRI(MCIF_WB_BUF_1_ADDR_C, MCIF_WB, inst),\
+ SRI(MCIF_WB_BUF_1_ADDR_C_OFFSET, MCIF_WB, inst),\
+ SRI(MCIF_WB_BUF_2_ADDR_Y, MCIF_WB, inst),\
+ SRI(MCIF_WB_BUF_2_ADDR_Y_OFFSET, MCIF_WB, inst),\
+ SRI(MCIF_WB_BUF_2_ADDR_C, MCIF_WB, inst),\
+ SRI(MCIF_WB_BUF_2_ADDR_C_OFFSET, MCIF_WB, inst),\
+ SRI(MCIF_WB_BUF_3_ADDR_Y, MCIF_WB, inst),\
+ SRI(MCIF_WB_BUF_3_ADDR_Y_OFFSET, MCIF_WB, inst),\
+ SRI(MCIF_WB_BUF_3_ADDR_C, MCIF_WB, inst),\
+ SRI(MCIF_WB_BUF_3_ADDR_C_OFFSET, MCIF_WB, inst),\
+ SRI(MCIF_WB_BUF_4_ADDR_Y, MCIF_WB, inst),\
+ SRI(MCIF_WB_BUF_4_ADDR_Y_OFFSET, MCIF_WB, inst),\
+ SRI(MCIF_WB_BUF_4_ADDR_C, MCIF_WB, inst),\
+ SRI(MCIF_WB_BUF_4_ADDR_C_OFFSET, MCIF_WB, inst),\
+ SRI(MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB, inst),\
+ SRI(MCIF_WB_NB_PSTATE_LATENCY_WATERMARK, MCIF_WB, inst),\
+ SRI(MCIF_WB_NB_PSTATE_CONTROL, MCIF_WB, inst),\
+ SRI(MCIF_WB_WATERMARK, MCIF_WB, inst),\
+ SRI(MCIF_WB_WARM_UP_CNTL, MCIF_WB, inst),\
+ SRI(MCIF_WB_BUF_LUMA_SIZE, MCIF_WB, inst),\
+ SRI(MCIF_WB_BUF_CHROMA_SIZE, MCIF_WB, inst)
+
+#define DWBC_COMMON_MASK_SH_LIST_DCN1_0(mask_sh) \
+ SF(CNV0_WB_ENABLE, WB_ENABLE, mask_sh),\
+ SF(CNV0_WB_EC_CONFIG, DISPCLK_R_WB_GATE_DIS, mask_sh),\
+ SF(CNV0_WB_EC_CONFIG, DISPCLK_G_WB_GATE_DIS, mask_sh),\
+ SF(CNV0_WB_EC_CONFIG, DISPCLK_G_WBSCL_GATE_DIS, mask_sh),\
+ SF(CNV0_WB_EC_CONFIG, WB_LB_LS_DIS, mask_sh),\
+ SF(CNV0_WB_EC_CONFIG, WB_LUT_LS_DIS, mask_sh),\
+ SF(CNV0_CNV_MODE, CNV_WINDOW_CROP_EN, mask_sh),\
+ SF(CNV0_CNV_MODE, CNV_STEREO_TYPE, mask_sh),\
+ SF(CNV0_CNV_MODE, CNV_INTERLACED_MODE, mask_sh),\
+ SF(CNV0_CNV_MODE, CNV_EYE_SELECTION, mask_sh),\
+ SF(CNV0_CNV_MODE, CNV_STEREO_POLARITY, mask_sh),\
+ SF(CNV0_CNV_MODE, CNV_INTERLACED_FIELD_ORDER, mask_sh),\
+ SF(CNV0_CNV_MODE, CNV_STEREO_SPLIT, mask_sh),\
+ SF(CNV0_CNV_MODE, CNV_NEW_CONTENT, mask_sh),\
+ SF(CNV0_CNV_MODE, CNV_FRAME_CAPTURE_EN, mask_sh),\
+ SF(CNV0_WB_SOFT_RESET, WB_SOFT_RESET, mask_sh),\
+ SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_ENABLE, mask_sh),\
+ SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUF_DUALSIZE_REQ, mask_sh),\
+ SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_INT_EN, mask_sh),\
+ SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_INT_ACK, mask_sh),\
+ SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_SLICE_INT_EN, mask_sh),\
+ SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_OVERRUN_INT_EN, mask_sh),\
+ SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_LOCK, mask_sh),\
+ SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_P_VMID, mask_sh),\
+ SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUF_ADDR_FENCE_EN, mask_sh),\
+ SF(MCIF_WB0_MCIF_WB_BUF_PITCH, MCIF_WB_BUF_LUMA_PITCH, mask_sh),\
+ SF(MCIF_WB0_MCIF_WB_BUF_PITCH, MCIF_WB_BUF_CHROMA_PITCH, mask_sh),\
+ SF(MCIF_WB0_MCIF_WB_ARBITRATION_CONTROL, MCIF_WB_CLIENT_ARBITRATION_SLICE, mask_sh),\
+ SF(MCIF_WB0_MCIF_WB_ARBITRATION_CONTROL, MCIF_WB_TIME_PER_PIXEL, mask_sh),\
+ SF(MCIF_WB0_MCIF_WB_SCLK_CHANGE, WM_CHANGE_ACK_FORCE_ON, mask_sh),\
+ SF(MCIF_WB0_MCIF_WB_SCLK_CHANGE, MCIF_WB_CLI_WATERMARK_MASK, mask_sh),\
+ SF(MCIF_WB0_MCIF_WB_BUF_1_ADDR_Y, MCIF_WB_BUF_1_ADDR_Y, mask_sh),\
+ SF(MCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_OFFSET, MCIF_WB_BUF_1_ADDR_Y_OFFSET, mask_sh),\
+ SF(MCIF_WB0_MCIF_WB_BUF_1_ADDR_C, MCIF_WB_BUF_1_ADDR_C, mask_sh),\
+ SF(MCIF_WB0_MCIF_WB_BUF_1_ADDR_C_OFFSET, MCIF_WB_BUF_1_ADDR_C_OFFSET, mask_sh),\
+ SF(MCIF_WB0_MCIF_WB_BUF_2_ADDR_Y, MCIF_WB_BUF_2_ADDR_Y, mask_sh),\
+ SF(MCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_OFFSET, MCIF_WB_BUF_2_ADDR_Y_OFFSET, mask_sh),\
+ SF(MCIF_WB0_MCIF_WB_BUF_2_ADDR_C, MCIF_WB_BUF_2_ADDR_C, mask_sh),\
+ SF(MCIF_WB0_MCIF_WB_BUF_2_ADDR_C_OFFSET, MCIF_WB_BUF_2_ADDR_C_OFFSET, mask_sh),\
+ SF(MCIF_WB0_MCIF_WB_BUF_3_ADDR_Y, MCIF_WB_BUF_3_ADDR_Y, mask_sh),\
+ SF(MCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_OFFSET, MCIF_WB_BUF_3_ADDR_Y_OFFSET, mask_sh),\
+ SF(MCIF_WB0_MCIF_WB_BUF_3_ADDR_C, MCIF_WB_BUF_3_ADDR_C, mask_sh),\
+ SF(MCIF_WB0_MCIF_WB_BUF_3_ADDR_C_OFFSET, MCIF_WB_BUF_3_ADDR_C_OFFSET, mask_sh),\
+ SF(MCIF_WB0_MCIF_WB_BUF_4_ADDR_Y, MCIF_WB_BUF_4_ADDR_Y, mask_sh),\
+ SF(MCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_OFFSET, MCIF_WB_BUF_4_ADDR_Y_OFFSET, mask_sh),\
+ SF(MCIF_WB0_MCIF_WB_BUF_4_ADDR_C, MCIF_WB_BUF_4_ADDR_C, mask_sh),\
+ SF(MCIF_WB0_MCIF_WB_BUF_4_ADDR_C_OFFSET, MCIF_WB_BUF_4_ADDR_C_OFFSET, mask_sh),\
+ SF(MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB_BUFMGR_VCE_LOCK_IGNORE, mask_sh),\
+ SF(MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB_BUFMGR_VCE_INT_EN, mask_sh),\
+ SF(MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB_BUFMGR_VCE_INT_ACK, mask_sh),\
+ SF(MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB_BUFMGR_VCE_SLICE_INT_EN, mask_sh),\
+ SF(MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB_BUFMGR_VCE_LOCK, mask_sh),\
+ SF(MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB_BUFMGR_SLICE_SIZE, mask_sh),\
+ SF(MCIF_WB0_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK, NB_PSTATE_CHANGE_REFRESH_WATERMARK, mask_sh),\
+ SF(MCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL, NB_PSTATE_CHANGE_URGENT_DURING_REQUEST, mask_sh),\
+ SF(MCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL, NB_PSTATE_CHANGE_FORCE_ON, mask_sh),\
+ SF(MCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL, NB_PSTATE_ALLOW_FOR_URGENT, mask_sh),\
+ SF(MCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL, NB_PSTATE_CHANGE_WATERMARK_MASK, mask_sh),\
+ SF(MCIF_WB0_MCIF_WB_WATERMARK, MCIF_WB_CLI_WATERMARK, mask_sh),\
+ SF(MCIF_WB0_MCIF_WB_WARM_UP_CNTL, MCIF_WB_PITCH_SIZE_WARMUP, mask_sh),\
+ SF(MCIF_WB0_MCIF_WB_BUF_LUMA_SIZE, MCIF_WB_BUF_LUMA_SIZE, mask_sh),\
+ SF(MCIF_WB0_MCIF_WB_BUF_CHROMA_SIZE, MCIF_WB_BUF_CHROMA_SIZE, mask_sh)
+
+#define DWBC_REG_FIELD_LIST(type) \
+ type WB_ENABLE;\
+ type DISPCLK_R_WB_GATE_DIS;\
+ type DISPCLK_G_WB_GATE_DIS;\
+ type DISPCLK_G_WBSCL_GATE_DIS;\
+ type WB_LB_LS_DIS;\
+ type WB_LB_SD_DIS;\
+ type WB_LUT_LS_DIS;\
+ type CNV_WINDOW_CROP_EN;\
+ type CNV_STEREO_TYPE;\
+ type CNV_INTERLACED_MODE;\
+ type CNV_EYE_SELECTION;\
+ type CNV_STEREO_POLARITY;\
+ type CNV_INTERLACED_FIELD_ORDER;\
+ type CNV_STEREO_SPLIT;\
+ type CNV_NEW_CONTENT;\
+ type CNV_FRAME_CAPTURE_EN;\
+ type WB_SOFT_RESET;\
+ type MCIF_WB_BUFMGR_ENABLE;\
+ type MCIF_WB_BUF_DUALSIZE_REQ;\
+ type MCIF_WB_BUFMGR_SW_INT_EN;\
+ type MCIF_WB_BUFMGR_SW_INT_ACK;\
+ type MCIF_WB_BUFMGR_SW_SLICE_INT_EN;\
+ type MCIF_WB_BUFMGR_SW_OVERRUN_INT_EN;\
+ type MCIF_WB_BUFMGR_SW_LOCK;\
+ type MCIF_WB_P_VMID;\
+ type MCIF_WB_BUF_ADDR_FENCE_EN;\
+ type MCIF_WB_BUF_LUMA_PITCH;\
+ type MCIF_WB_BUF_CHROMA_PITCH;\
+ type MCIF_WB_CLIENT_ARBITRATION_SLICE;\
+ type MCIF_WB_TIME_PER_PIXEL;\
+ type WM_CHANGE_ACK_FORCE_ON;\
+ type MCIF_WB_CLI_WATERMARK_MASK;\
+ type MCIF_WB_BUF_1_ADDR_Y;\
+ type MCIF_WB_BUF_1_ADDR_Y_OFFSET;\
+ type MCIF_WB_BUF_1_ADDR_C;\
+ type MCIF_WB_BUF_1_ADDR_C_OFFSET;\
+ type MCIF_WB_BUF_2_ADDR_Y;\
+ type MCIF_WB_BUF_2_ADDR_Y_OFFSET;\
+ type MCIF_WB_BUF_2_ADDR_C;\
+ type MCIF_WB_BUF_2_ADDR_C_OFFSET;\
+ type MCIF_WB_BUF_3_ADDR_Y;\
+ type MCIF_WB_BUF_3_ADDR_Y_OFFSET;\
+ type MCIF_WB_BUF_3_ADDR_C;\
+ type MCIF_WB_BUF_3_ADDR_C_OFFSET;\
+ type MCIF_WB_BUF_4_ADDR_Y;\
+ type MCIF_WB_BUF_4_ADDR_Y_OFFSET;\
+ type MCIF_WB_BUF_4_ADDR_C;\
+ type MCIF_WB_BUF_4_ADDR_C_OFFSET;\
+ type MCIF_WB_BUFMGR_VCE_LOCK_IGNORE;\
+ type MCIF_WB_BUFMGR_VCE_INT_EN;\
+ type MCIF_WB_BUFMGR_VCE_INT_ACK;\
+ type MCIF_WB_BUFMGR_VCE_SLICE_INT_EN;\
+ type MCIF_WB_BUFMGR_VCE_LOCK;\
+ type MCIF_WB_BUFMGR_SLICE_SIZE;\
+ type NB_PSTATE_CHANGE_REFRESH_WATERMARK;\
+ type NB_PSTATE_CHANGE_URGENT_DURING_REQUEST;\
+ type NB_PSTATE_CHANGE_FORCE_ON;\
+ type NB_PSTATE_ALLOW_FOR_URGENT;\
+ type NB_PSTATE_CHANGE_WATERMARK_MASK;\
+ type MCIF_WB_CLI_WATERMARK;\
+ type MCIF_WB_CLI_CLOCK_GATER_OVERRIDE;\
+ type MCIF_WB_PITCH_SIZE_WARMUP;\
+ type MCIF_WB_BUF_LUMA_SIZE;\
+ type MCIF_WB_BUF_CHROMA_SIZE;\
+
+struct dcn10_dwbc_registers {
+ uint32_t WB_ENABLE;
+ uint32_t WB_EC_CONFIG;
+ uint32_t CNV_MODE;
+ uint32_t WB_SOFT_RESET;
+ uint32_t MCIF_WB_BUFMGR_SW_CONTROL;
+ uint32_t MCIF_WB_BUF_PITCH;
+ uint32_t MCIF_WB_ARBITRATION_CONTROL;
+ uint32_t MCIF_WB_SCLK_CHANGE;
+ uint32_t MCIF_WB_BUF_1_ADDR_Y;
+ uint32_t MCIF_WB_BUF_1_ADDR_Y_OFFSET;
+ uint32_t MCIF_WB_BUF_1_ADDR_C;
+ uint32_t MCIF_WB_BUF_1_ADDR_C_OFFSET;
+ uint32_t MCIF_WB_BUF_2_ADDR_Y;
+ uint32_t MCIF_WB_BUF_2_ADDR_Y_OFFSET;
+ uint32_t MCIF_WB_BUF_2_ADDR_C;
+ uint32_t MCIF_WB_BUF_2_ADDR_C_OFFSET;
+ uint32_t MCIF_WB_BUF_3_ADDR_Y;
+ uint32_t MCIF_WB_BUF_3_ADDR_Y_OFFSET;
+ uint32_t MCIF_WB_BUF_3_ADDR_C;
+ uint32_t MCIF_WB_BUF_3_ADDR_C_OFFSET;
+ uint32_t MCIF_WB_BUF_4_ADDR_Y;
+ uint32_t MCIF_WB_BUF_4_ADDR_Y_OFFSET;
+ uint32_t MCIF_WB_BUF_4_ADDR_C;
+ uint32_t MCIF_WB_BUF_4_ADDR_C_OFFSET;
+ uint32_t MCIF_WB_BUFMGR_VCE_CONTROL;
+ uint32_t MCIF_WB_NB_PSTATE_LATENCY_WATERMARK;
+ uint32_t MCIF_WB_NB_PSTATE_CONTROL;
+ uint32_t MCIF_WB_WATERMARK;
+ uint32_t MCIF_WB_WARM_UP_CNTL;
+ uint32_t MCIF_WB_BUF_LUMA_SIZE;
+ uint32_t MCIF_WB_BUF_CHROMA_SIZE;
+};
+struct dcn10_dwbc_mask {
+ DWBC_REG_FIELD_LIST(uint32_t)
+};
+struct dcn10_dwbc_shift {
+ DWBC_REG_FIELD_LIST(uint8_t)
+};
+struct dcn10_dwbc {
+ struct dwbc base;
+ const struct dcn10_dwbc_registers *dwbc_regs;
+ const struct dcn10_dwbc_shift *dwbc_shift;
+ const struct dcn10_dwbc_mask *dwbc_mask;
+};
+
+void dcn10_dwbc_construct(struct dcn10_dwbc *dwbc10,
+ struct dc_context *ctx,
+ const struct dcn10_dwbc_registers *dwbc_regs,
+ const struct dcn10_dwbc_shift *dwbc_shift,
+ const struct dcn10_dwbc_mask *dwbc_mask,
+ int inst);
+
+#endif
+
+#endif
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c
new file mode 100644
index 000000000000..14bdb63950af
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c
@@ -0,0 +1,315 @@
+/*
+ * Copyright 2012-17 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+
+#include "reg_helper.h"
+#include "resource.h"
+#include "dwb.h"
+#include "dcn20_dwb.h"
+
+
+#define REG(reg)\
+ dwbc20->dwbc_regs->reg
+
+#define CTX \
+ dwbc20->base.ctx
+
+#undef FN
+#define FN(reg_name, field_name) \
+ dwbc20->dwbc_shift->field_name, dwbc20->dwbc_mask->field_name
+
+enum dwb_outside_pix_strategy {
+ DWB_OUTSIDE_PIX_STRATEGY_BLACK = 0,
+ DWB_OUTSIDE_PIX_STRATEGY_EDGE = 1
+};
+
+static bool dwb2_get_caps(struct dwbc *dwbc, struct dwb_caps *caps)
+{
+ if (caps) {
+ caps->adapter_id = 0; /* we only support 1 adapter currently */
+ caps->hw_version = DCN_VERSION_2_0;
+ caps->num_pipes = 1;
+ memset(&caps->reserved, 0, sizeof(caps->reserved));
+ memset(&caps->reserved2, 0, sizeof(caps->reserved2));
+ caps->sw_version = dwb_ver_1_0;
+ caps->caps.support_dwb = true;
+ caps->caps.support_ogam = false;
+ caps->caps.support_wbscl = false;
+ caps->caps.support_ocsc = false;
+ return true;
+ } else {
+ return false;
+ }
+}
+
+void dwb2_config_dwb_cnv(struct dwbc *dwbc, struct dc_dwb_params *params)
+{
+ struct dcn20_dwbc *dwbc20 = TO_DCN20_DWBC(dwbc);
+
+ /* Set DWB source size */
+ REG_UPDATE_2(CNV_SOURCE_SIZE, CNV_SOURCE_WIDTH, params->cnv_params.src_width,
+ CNV_SOURCE_HEIGHT, params->cnv_params.src_height);
+
+ /* source size is not equal the source size, then enable cropping. */
+ if (params->cnv_params.crop_en) {
+ REG_UPDATE(CNV_MODE, CNV_WINDOW_CROP_EN, 1);
+ REG_UPDATE(CNV_WINDOW_START, CNV_WINDOW_START_X, params->cnv_params.crop_x);
+ REG_UPDATE(CNV_WINDOW_START, CNV_WINDOW_START_Y, params->cnv_params.crop_y);
+ REG_UPDATE(CNV_WINDOW_SIZE, CNV_WINDOW_WIDTH, params->cnv_params.crop_width);
+ REG_UPDATE(CNV_WINDOW_SIZE, CNV_WINDOW_HEIGHT, params->cnv_params.crop_height);
+ } else {
+ REG_UPDATE(CNV_MODE, CNV_WINDOW_CROP_EN, 0);
+ }
+
+ /* Set CAPTURE_RATE */
+ REG_UPDATE(CNV_MODE, CNV_FRAME_CAPTURE_RATE, params->capture_rate);
+
+ /* Set CNV output pixel depth */
+ REG_UPDATE(CNV_MODE, CNV_OUT_BPC, params->cnv_params.cnv_out_bpc);
+}
+
+static bool dwb2_enable(struct dwbc *dwbc, struct dc_dwb_params *params)
+{
+ struct dcn20_dwbc *dwbc20 = TO_DCN20_DWBC(dwbc);
+
+ /* Only chroma scaling (sub-sampling) is supported in DCN2 */
+ if ((params->cnv_params.src_width != params->dest_width)
+ || (params->cnv_params.src_height != params->dest_height)) {
+ return false;
+ }
+
+ /* disable power gating */
+ //REG_UPDATE_5(WB_EC_CONFIG, DISPCLK_R_WB_GATE_DIS, 1,
+ // DISPCLK_G_WB_GATE_DIS, 1, DISPCLK_G_WBSCL_GATE_DIS, 1,
+ // WB_LB_LS_DIS, 1, WB_LUT_LS_DIS, 1);
+
+ /* Set WB_ENABLE (not double buffered; capture not enabled) */
+ REG_UPDATE(WB_ENABLE, WB_ENABLE, 1);
+
+ /* Set CNV parameters */
+ dwb2_config_dwb_cnv(dwbc, params);
+
+ /* Set scaling parameters */
+ dwb2_set_scaler(dwbc, params);
+
+ /* Enable DWB capture enable (double buffered) */
+ REG_UPDATE(CNV_MODE, CNV_FRAME_CAPTURE_EN, DWB_FRAME_CAPTURE_ENABLE);
+
+ // disable warmup
+ REG_UPDATE(WB_WARM_UP_MODE_CTL1, GMC_WARM_UP_ENABLE, 0);
+
+ return true;
+}
+
+bool dwb2_disable(struct dwbc *dwbc)
+{
+ struct dcn20_dwbc *dwbc20 = TO_DCN20_DWBC(dwbc);
+
+ /* disable CNV */
+ REG_UPDATE(CNV_MODE, CNV_FRAME_CAPTURE_EN, DWB_FRAME_CAPTURE_DISABLE);
+
+ /* disable WB */
+ REG_UPDATE(WB_ENABLE, WB_ENABLE, 0);
+
+ /* soft reset */
+ REG_UPDATE(WB_SOFT_RESET, WB_SOFT_RESET, 1);
+ REG_UPDATE(WB_SOFT_RESET, WB_SOFT_RESET, 0);
+
+ /* enable power gating */
+ //REG_UPDATE_5(WB_EC_CONFIG, DISPCLK_R_WB_GATE_DIS, 0,
+ // DISPCLK_G_WB_GATE_DIS, 0, DISPCLK_G_WBSCL_GATE_DIS, 0,
+ // WB_LB_LS_DIS, 0, WB_LUT_LS_DIS, 0);
+
+ return true;
+}
+
+static bool dwb2_update(struct dwbc *dwbc, struct dc_dwb_params *params)
+{
+ struct dcn20_dwbc *dwbc20 = TO_DCN20_DWBC(dwbc);
+ unsigned int pre_locked;
+
+ /* Only chroma scaling (sub-sampling) is supported in DCN2 */
+ if ((params->cnv_params.src_width != params->dest_width)
+ || (params->cnv_params.src_height != params->dest_height)) {
+ return false;
+ }
+
+ /*
+ * Check if the caller has already locked CNV registers.
+ * If so: assume the caller will unlock, so don't touch the lock.
+ * If not: lock them for this update, then unlock after the
+ * update is complete.
+ */
+ REG_GET(CNV_UPDATE, CNV_UPDATE_LOCK, &pre_locked);
+
+ if (pre_locked == 0) {
+ /* Lock DWB registers */
+ REG_UPDATE(CNV_UPDATE, CNV_UPDATE_LOCK, 1);
+ }
+
+ /* Set CNV parameters */
+ dwb2_config_dwb_cnv(dwbc, params);
+
+ /* Set scaling parameters */
+ dwb2_set_scaler(dwbc, params);
+
+ if (pre_locked == 0) {
+ /* Unlock DWB registers */
+ REG_UPDATE(CNV_UPDATE, CNV_UPDATE_LOCK, 0);
+ }
+
+ return true;
+}
+
+bool dwb2_is_enabled(struct dwbc *dwbc)
+{
+ struct dcn20_dwbc *dwbc20 = TO_DCN20_DWBC(dwbc);
+ unsigned int wb_enabled = 0;
+ unsigned int cnv_frame_capture_en = 0;
+
+ REG_GET(WB_ENABLE, WB_ENABLE, &wb_enabled);
+ REG_GET(CNV_MODE, CNV_FRAME_CAPTURE_EN, &cnv_frame_capture_en);
+
+ return ((wb_enabled != 0) && (cnv_frame_capture_en != 0));
+}
+
+void dwb2_set_stereo(struct dwbc *dwbc,
+ struct dwb_stereo_params *stereo_params)
+{
+ struct dcn20_dwbc *dwbc20 = TO_DCN20_DWBC(dwbc);
+
+ if (stereo_params->stereo_enabled) {
+ REG_UPDATE(CNV_MODE, CNV_STEREO_TYPE, stereo_params->stereo_type);
+ REG_UPDATE(CNV_MODE, CNV_EYE_SELECTION, stereo_params->stereo_eye_select);
+ REG_UPDATE(CNV_MODE, CNV_STEREO_POLARITY, stereo_params->stereo_polarity);
+ } else {
+ REG_UPDATE(CNV_MODE, CNV_EYE_SELECTION, 0);
+ }
+}
+
+void dwb2_set_new_content(struct dwbc *dwbc,
+ bool is_new_content)
+{
+ struct dcn20_dwbc *dwbc20 = TO_DCN20_DWBC(dwbc);
+
+ REG_UPDATE(CNV_MODE, CNV_NEW_CONTENT, is_new_content);
+}
+
+static void dwb2_set_warmup(struct dwbc *dwbc,
+ struct dwb_warmup_params *warmup_params)
+{
+ struct dcn20_dwbc *dwbc20 = TO_DCN20_DWBC(dwbc);
+
+ REG_UPDATE(WB_WARM_UP_MODE_CTL1, GMC_WARM_UP_ENABLE, warmup_params->warmup_en);
+ REG_UPDATE(WB_WARM_UP_MODE_CTL1, WIDTH_WARMUP, warmup_params->warmup_width);
+ REG_UPDATE(WB_WARM_UP_MODE_CTL1, HEIGHT_WARMUP, warmup_params->warmup_height);
+
+ REG_UPDATE(WB_WARM_UP_MODE_CTL2, DATA_VALUE_WARMUP, warmup_params->warmup_data);
+ REG_UPDATE(WB_WARM_UP_MODE_CTL2, MODE_WARMUP, warmup_params->warmup_mode);
+ REG_UPDATE(WB_WARM_UP_MODE_CTL2, DATA_DEPTH_WARMUP, warmup_params->warmup_depth);
+}
+
+void dwb2_set_scaler(struct dwbc *dwbc, struct dc_dwb_params *params)
+{
+ struct dcn20_dwbc *dwbc20 = TO_DCN20_DWBC(dwbc);
+
+ /* Program scaling mode */
+ REG_UPDATE_2(WBSCL_MODE, WBSCL_MODE, params->out_format,
+ WBSCL_OUT_BIT_DEPTH, params->output_depth);
+
+ if (params->out_format != dwb_scaler_mode_bypass444) {
+ /* Program output size */
+ REG_UPDATE(WBSCL_DEST_SIZE, WBSCL_DEST_WIDTH, params->dest_width);
+ REG_UPDATE(WBSCL_DEST_SIZE, WBSCL_DEST_HEIGHT, params->dest_height);
+
+ /* Program round offsets */
+ REG_UPDATE(WBSCL_ROUND_OFFSET, WBSCL_ROUND_OFFSET_Y_RGB, 0x40);
+ REG_UPDATE(WBSCL_ROUND_OFFSET, WBSCL_ROUND_OFFSET_CBCR, 0x200);
+
+ /* Program clamp values */
+ REG_UPDATE(WBSCL_CLAMP_Y_RGB, WBSCL_CLAMP_UPPER_Y_RGB, 0x3fe);
+ REG_UPDATE(WBSCL_CLAMP_Y_RGB, WBSCL_CLAMP_LOWER_Y_RGB, 0x1);
+ REG_UPDATE(WBSCL_CLAMP_CBCR, WBSCL_CLAMP_UPPER_CBCR, 0x3fe);
+ REG_UPDATE(WBSCL_CLAMP_CBCR, WBSCL_CLAMP_LOWER_CBCR, 0x1);
+
+ /* Program outside pixel strategy to use edge pixels */
+ REG_UPDATE(WBSCL_OUTSIDE_PIX_STRATEGY, WBSCL_OUTSIDE_PIX_STRATEGY, DWB_OUTSIDE_PIX_STRATEGY_EDGE);
+
+ if (params->cnv_params.crop_en) {
+ /* horizontal scale */
+ dwb_program_horz_scalar(dwbc20, params->cnv_params.crop_width,
+ params->dest_width,
+ params->scaler_taps);
+
+ /* vertical scale */
+ dwb_program_vert_scalar(dwbc20, params->cnv_params.crop_height,
+ params->dest_height,
+ params->scaler_taps,
+ params->subsample_position);
+ } else {
+ /* horizontal scale */
+ dwb_program_horz_scalar(dwbc20, params->cnv_params.src_width,
+ params->dest_width,
+ params->scaler_taps);
+
+ /* vertical scale */
+ dwb_program_vert_scalar(dwbc20, params->cnv_params.src_height,
+ params->dest_height,
+ params->scaler_taps,
+ params->subsample_position);
+ }
+ }
+
+}
+
+const struct dwbc_funcs dcn20_dwbc_funcs = {
+ .get_caps = dwb2_get_caps,
+ .enable = dwb2_enable,
+ .disable = dwb2_disable,
+ .update = dwb2_update,
+ .is_enabled = dwb2_is_enabled,
+ .set_stereo = dwb2_set_stereo,
+ .set_new_content = dwb2_set_new_content,
+ .set_warmup = dwb2_set_warmup,
+ .dwb_set_scaler = dwb2_set_scaler,
+};
+
+void dcn20_dwbc_construct(struct dcn20_dwbc *dwbc20,
+ struct dc_context *ctx,
+ const struct dcn20_dwbc_registers *dwbc_regs,
+ const struct dcn20_dwbc_shift *dwbc_shift,
+ const struct dcn20_dwbc_mask *dwbc_mask,
+ int inst)
+{
+ dwbc20->base.ctx = ctx;
+
+ dwbc20->base.inst = inst;
+ dwbc20->base.funcs = &dcn20_dwbc_funcs;
+
+ dwbc20->dwbc_regs = dwbc_regs;
+ dwbc20->dwbc_shift = dwbc_shift;
+ dwbc20->dwbc_mask = dwbc_mask;
+}
+
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h
new file mode 100644
index 000000000000..a85ed228dfc2
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h
@@ -0,0 +1,458 @@
+/* Copyright 2012-17 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+#ifndef __DC_DWBC_DCN20_H__
+#define __DC_DWBC_DCN20_H__
+
+#define TO_DCN20_DWBC(dwbc_base) \
+ container_of(dwbc_base, struct dcn20_dwbc, base)
+
+/* DCN */
+#define BASE_INNER(seg) \
+ DCE_BASE__INST0_SEG ## seg
+
+#define BASE(seg) \
+ BASE_INNER(seg)
+
+#define SR(reg_name)\
+ .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \
+ mm ## reg_name
+
+#define SRI(reg_name, block, id)\
+ .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
+ mm ## block ## id ## _ ## reg_name
+
+#define SRI2(reg_name, block, id)\
+ .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \
+ mm ## reg_name
+
+#define SRII(reg_name, block, id)\
+ .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
+ mm ## block ## id ## _ ## reg_name
+
+#define SF(reg_name, field_name, post_fix)\
+ .field_name = reg_name ## __ ## field_name ## post_fix
+
+
+#define DWBC_COMMON_REG_LIST_DCN2_0(inst) \
+ SRI2(WB_ENABLE, CNV, inst),\
+ SRI2(WB_EC_CONFIG, CNV, inst),\
+ SRI2(CNV_MODE, CNV, inst),\
+ SRI2(CNV_WINDOW_START, CNV, inst),\
+ SRI2(CNV_WINDOW_SIZE, CNV, inst),\
+ SRI2(CNV_UPDATE, CNV, inst),\
+ SRI2(CNV_SOURCE_SIZE, CNV, inst),\
+ SRI2(CNV_TEST_CNTL, CNV, inst),\
+ SRI2(CNV_TEST_CRC_RED, CNV, inst),\
+ SRI2(CNV_TEST_CRC_GREEN, CNV, inst),\
+ SRI2(CNV_TEST_CRC_BLUE, CNV, inst),\
+ SRI2(WBSCL_COEF_RAM_SELECT, WBSCL, inst),\
+ SRI2(WBSCL_COEF_RAM_TAP_DATA, WBSCL, inst),\
+ SRI2(WBSCL_MODE, WBSCL, inst),\
+ SRI2(WBSCL_TAP_CONTROL, WBSCL, inst),\
+ SRI2(WBSCL_DEST_SIZE, WBSCL, inst),\
+ SRI2(WBSCL_HORZ_FILTER_SCALE_RATIO, WBSCL, inst),\
+ SRI2(WBSCL_HORZ_FILTER_INIT_Y_RGB, WBSCL, inst),\
+ SRI2(WBSCL_HORZ_FILTER_INIT_CBCR, WBSCL, inst),\
+ SRI2(WBSCL_VERT_FILTER_SCALE_RATIO, WBSCL, inst),\
+ SRI2(WBSCL_VERT_FILTER_INIT_Y_RGB, WBSCL, inst),\
+ SRI2(WBSCL_VERT_FILTER_INIT_CBCR, WBSCL, inst),\
+ SRI2(WBSCL_ROUND_OFFSET, WBSCL, inst),\
+ SRI2(WBSCL_OVERFLOW_STATUS, WBSCL, inst),\
+ SRI2(WBSCL_COEF_RAM_CONFLICT_STATUS, WBSCL, inst),\
+ SRI2(WBSCL_TEST_CNTL, WBSCL, inst),\
+ SRI2(WBSCL_TEST_CRC_RED, WBSCL, inst),\
+ SRI2(WBSCL_TEST_CRC_GREEN, WBSCL, inst),\
+ SRI2(WBSCL_TEST_CRC_BLUE, WBSCL, inst),\
+ SRI2(WBSCL_BACKPRESSURE_CNT_EN, WBSCL, inst),\
+ SRI2(WB_MCIF_BACKPRESSURE_CNT, WBSCL, inst),\
+ SRI2(WBSCL_CLAMP_Y_RGB, WBSCL, inst),\
+ SRI2(WBSCL_CLAMP_CBCR, WBSCL, inst),\
+ SRI2(WBSCL_OUTSIDE_PIX_STRATEGY, WBSCL, inst),\
+ SRI2(WBSCL_OUTSIDE_PIX_STRATEGY_CBCR, WBSCL, inst),\
+ SRI2(WBSCL_DEBUG, WBSCL, inst),\
+ SRI2(WBSCL_TEST_DEBUG_INDEX, WBSCL, inst),\
+ SRI2(WBSCL_TEST_DEBUG_DATA, WBSCL, inst),\
+ SRI2(WB_DEBUG_CTRL, CNV, inst),\
+ SRI2(WB_DBG_MODE, CNV, inst),\
+ SRI2(WB_HW_DEBUG, CNV, inst),\
+ SRI2(CNV_TEST_DEBUG_INDEX, CNV, inst),\
+ SRI2(CNV_TEST_DEBUG_DATA, CNV, inst),\
+ SRI2(WB_SOFT_RESET, CNV, inst),\
+ SRI2(WB_WARM_UP_MODE_CTL1, CNV, inst),\
+ SRI2(WB_WARM_UP_MODE_CTL2, CNV, inst)
+
+#define DWBC_COMMON_MASK_SH_LIST_DCN2_0(mask_sh) \
+ SF(WB_ENABLE, WB_ENABLE, mask_sh),\
+ SF(WB_EC_CONFIG, DISPCLK_R_WB_GATE_DIS, mask_sh),\
+ SF(WB_EC_CONFIG, DISPCLK_G_WB_GATE_DIS, mask_sh),\
+ SF(WB_EC_CONFIG, DISPCLK_G_WBSCL_GATE_DIS, mask_sh),\
+ SF(WB_EC_CONFIG, WB_TEST_CLK_SEL, mask_sh),\
+ SF(WB_EC_CONFIG, WB_LB_LS_DIS, mask_sh),\
+ SF(WB_EC_CONFIG, WB_LB_SD_DIS, mask_sh),\
+ SF(WB_EC_CONFIG, WB_LUT_LS_DIS, mask_sh),\
+ SF(WB_EC_CONFIG, WBSCL_LB_MEM_PWR_MODE_SEL, mask_sh),\
+ SF(WB_EC_CONFIG, WBSCL_LB_MEM_PWR_DIS, mask_sh),\
+ SF(WB_EC_CONFIG, WBSCL_LB_MEM_PWR_FORCE, mask_sh),\
+ SF(WB_EC_CONFIG, WBSCL_LB_MEM_PWR_STATE, mask_sh),\
+ SF(WB_EC_CONFIG, WB_RAM_PW_SAVE_MODE, mask_sh),\
+ SF(WB_EC_CONFIG, WBSCL_LUT_MEM_PWR_STATE, mask_sh),\
+ SF(CNV_MODE, CNV_OUT_BPC, mask_sh),\
+ SF(CNV_MODE, CNV_FRAME_CAPTURE_RATE, mask_sh),\
+ SF(CNV_MODE, CNV_WINDOW_CROP_EN, mask_sh),\
+ SF(CNV_MODE, CNV_STEREO_TYPE, mask_sh),\
+ SF(CNV_MODE, CNV_INTERLACED_MODE, mask_sh),\
+ SF(CNV_MODE, CNV_EYE_SELECTION, mask_sh),\
+ SF(CNV_MODE, CNV_STEREO_POLARITY, mask_sh),\
+ SF(CNV_MODE, CNV_INTERLACED_FIELD_ORDER, mask_sh),\
+ SF(CNV_MODE, CNV_STEREO_SPLIT, mask_sh),\
+ SF(CNV_MODE, CNV_NEW_CONTENT, mask_sh),\
+ SF(CNV_MODE, CNV_FRAME_CAPTURE_EN_CURRENT, mask_sh),\
+ SF(CNV_MODE, CNV_FRAME_CAPTURE_EN, mask_sh),\
+ SF(CNV_WINDOW_START, CNV_WINDOW_START_X, mask_sh),\
+ SF(CNV_WINDOW_START, CNV_WINDOW_START_Y, mask_sh),\
+ SF(CNV_WINDOW_SIZE, CNV_WINDOW_WIDTH, mask_sh),\
+ SF(CNV_WINDOW_SIZE, CNV_WINDOW_HEIGHT, mask_sh),\
+ SF(CNV_UPDATE, CNV_UPDATE_PENDING, mask_sh),\
+ SF(CNV_UPDATE, CNV_UPDATE_TAKEN, mask_sh),\
+ SF(CNV_UPDATE, CNV_UPDATE_LOCK, mask_sh),\
+ SF(CNV_SOURCE_SIZE, CNV_SOURCE_WIDTH, mask_sh),\
+ SF(CNV_SOURCE_SIZE, CNV_SOURCE_HEIGHT, mask_sh),\
+ SF(CNV_TEST_CNTL, CNV_TEST_CRC_EN, mask_sh),\
+ SF(CNV_TEST_CNTL, CNV_TEST_CRC_CONT_EN, mask_sh),\
+ SF(CNV_TEST_CRC_RED, CNV_TEST_CRC_RED_MASK, mask_sh),\
+ SF(CNV_TEST_CRC_RED, CNV_TEST_CRC_SIG_RED, mask_sh),\
+ SF(CNV_TEST_CRC_GREEN, CNV_TEST_CRC_GREEN_MASK, mask_sh),\
+ SF(CNV_TEST_CRC_GREEN, CNV_TEST_CRC_SIG_GREEN, mask_sh),\
+ SF(CNV_TEST_CRC_BLUE, CNV_TEST_CRC_BLUE_MASK, mask_sh),\
+ SF(CNV_TEST_CRC_BLUE, CNV_TEST_CRC_SIG_BLUE, mask_sh),\
+ SF(WB_DEBUG_CTRL, WB_DEBUG_EN, mask_sh),\
+ SF(WB_DEBUG_CTRL, WB_DEBUG_SEL, mask_sh),\
+ SF(WB_DBG_MODE, WB_DBG_MODE_EN, mask_sh),\
+ SF(WB_DBG_MODE, WB_DBG_DIN_FMT, mask_sh),\
+ SF(WB_DBG_MODE, WB_DBG_36MODE, mask_sh),\
+ SF(WB_DBG_MODE, WB_DBG_CMAP, mask_sh),\
+ SF(WB_DBG_MODE, WB_DBG_PXLRATE_ERROR, mask_sh),\
+ SF(WB_DBG_MODE, WB_DBG_SOURCE_WIDTH, mask_sh),\
+ SF(WB_HW_DEBUG, WB_HW_DEBUG, mask_sh),\
+ SF(WB_SOFT_RESET, WB_SOFT_RESET, mask_sh),\
+ SF(CNV_TEST_DEBUG_INDEX, CNV_TEST_DEBUG_INDEX, mask_sh),\
+ SF(CNV_TEST_DEBUG_INDEX, CNV_TEST_DEBUG_WRITE_EN, mask_sh),\
+ SF(CNV_TEST_DEBUG_DATA, CNV_TEST_DEBUG_DATA, mask_sh),\
+ SF(WBSCL_COEF_RAM_SELECT, WBSCL_COEF_RAM_TAP_PAIR_IDX, mask_sh),\
+ SF(WBSCL_COEF_RAM_SELECT, WBSCL_COEF_RAM_PHASE, mask_sh),\
+ SF(WBSCL_COEF_RAM_SELECT, WBSCL_COEF_RAM_FILTER_TYPE, mask_sh),\
+ SF(WBSCL_COEF_RAM_TAP_DATA, WBSCL_COEF_RAM_EVEN_TAP_COEF, mask_sh),\
+ SF(WBSCL_COEF_RAM_TAP_DATA, WBSCL_COEF_RAM_EVEN_TAP_COEF_EN, mask_sh),\
+ SF(WBSCL_COEF_RAM_TAP_DATA, WBSCL_COEF_RAM_ODD_TAP_COEF, mask_sh),\
+ SF(WBSCL_COEF_RAM_TAP_DATA, WBSCL_COEF_RAM_ODD_TAP_COEF_EN, mask_sh),\
+ SF(WBSCL_MODE, WBSCL_MODE, mask_sh),\
+ SF(WBSCL_MODE, WBSCL_OUT_BIT_DEPTH, mask_sh),\
+ SF(WBSCL_TAP_CONTROL, WBSCL_V_NUM_OF_TAPS_Y_RGB, mask_sh),\
+ SF(WBSCL_TAP_CONTROL, WBSCL_V_NUM_OF_TAPS_CBCR, mask_sh),\
+ SF(WBSCL_TAP_CONTROL, WBSCL_H_NUM_OF_TAPS_Y_RGB, mask_sh),\
+ SF(WBSCL_TAP_CONTROL, WBSCL_H_NUM_OF_TAPS_CBCR, mask_sh),\
+ SF(WBSCL_DEST_SIZE, WBSCL_DEST_HEIGHT, mask_sh),\
+ SF(WBSCL_DEST_SIZE, WBSCL_DEST_WIDTH, mask_sh),\
+ SF(WBSCL_HORZ_FILTER_SCALE_RATIO, WBSCL_H_SCALE_RATIO, mask_sh),\
+ SF(WBSCL_HORZ_FILTER_INIT_Y_RGB, WBSCL_H_INIT_FRAC_Y_RGB, mask_sh),\
+ SF(WBSCL_HORZ_FILTER_INIT_Y_RGB, WBSCL_H_INIT_INT_Y_RGB, mask_sh),\
+ SF(WBSCL_HORZ_FILTER_INIT_CBCR, WBSCL_H_INIT_FRAC_CBCR, mask_sh),\
+ SF(WBSCL_HORZ_FILTER_INIT_CBCR, WBSCL_H_INIT_INT_CBCR, mask_sh),\
+ SF(WBSCL_VERT_FILTER_SCALE_RATIO, WBSCL_V_SCALE_RATIO, mask_sh),\
+ SF(WBSCL_VERT_FILTER_INIT_Y_RGB, WBSCL_V_INIT_FRAC_Y_RGB, mask_sh),\
+ SF(WBSCL_VERT_FILTER_INIT_Y_RGB, WBSCL_V_INIT_INT_Y_RGB, mask_sh),\
+ SF(WBSCL_VERT_FILTER_INIT_CBCR, WBSCL_V_INIT_FRAC_CBCR, mask_sh),\
+ SF(WBSCL_VERT_FILTER_INIT_CBCR, WBSCL_V_INIT_INT_CBCR, mask_sh),\
+ SF(WBSCL_ROUND_OFFSET, WBSCL_ROUND_OFFSET_Y_RGB, mask_sh),\
+ SF(WBSCL_ROUND_OFFSET, WBSCL_ROUND_OFFSET_CBCR, mask_sh),\
+ SF(WBSCL_OVERFLOW_STATUS, WBSCL_DATA_OVERFLOW_FLAG, mask_sh),\
+ SF(WBSCL_OVERFLOW_STATUS, WBSCL_DATA_OVERFLOW_ACK, mask_sh),\
+ SF(WBSCL_OVERFLOW_STATUS, WBSCL_DATA_OVERFLOW_MASK, mask_sh),\
+ SF(WBSCL_OVERFLOW_STATUS, WBSCL_DATA_OVERFLOW_INT_STATUS, mask_sh),\
+ SF(WBSCL_OVERFLOW_STATUS, WBSCL_DATA_OVERFLOW_INT_TYPE, mask_sh),\
+ SF(WBSCL_COEF_RAM_CONFLICT_STATUS, WBSCL_HOST_CONFLICT_FLAG, mask_sh),\
+ SF(WBSCL_COEF_RAM_CONFLICT_STATUS, WBSCL_HOST_CONFLICT_ACK, mask_sh),\
+ SF(WBSCL_COEF_RAM_CONFLICT_STATUS, WBSCL_HOST_CONFLICT_MASK, mask_sh),\
+ SF(WBSCL_COEF_RAM_CONFLICT_STATUS, WBSCL_HOST_CONFLICT_INT_STATUS, mask_sh),\
+ SF(WBSCL_COEF_RAM_CONFLICT_STATUS, WBSCL_HOST_CONFLICT_INT_TYPE, mask_sh),\
+ SF(WBSCL_TEST_CNTL, WBSCL_TEST_CRC_EN, mask_sh),\
+ SF(WBSCL_TEST_CNTL, WBSCL_TEST_CRC_CONT_EN, mask_sh),\
+ SF(WBSCL_TEST_CRC_RED, WBSCL_TEST_CRC_RED_MASK, mask_sh),\
+ SF(WBSCL_TEST_CRC_RED, WBSCL_TEST_CRC_SIG_RED, mask_sh),\
+ SF(WBSCL_TEST_CRC_GREEN, WBSCL_TEST_CRC_GREEN_MASK, mask_sh),\
+ SF(WBSCL_TEST_CRC_GREEN, WBSCL_TEST_CRC_SIG_GREEN, mask_sh),\
+ SF(WBSCL_TEST_CRC_BLUE, WBSCL_TEST_CRC_BLUE_MASK, mask_sh),\
+ SF(WBSCL_TEST_CRC_BLUE, WBSCL_TEST_CRC_SIG_BLUE, mask_sh),\
+ SF(WBSCL_BACKPRESSURE_CNT_EN, WBSCL_BACKPRESSURE_CNT_EN, mask_sh),\
+ SF(WB_MCIF_BACKPRESSURE_CNT, WB_MCIF_Y_MAX_BACKPRESSURE, mask_sh),\
+ SF(WB_MCIF_BACKPRESSURE_CNT, WB_MCIF_C_MAX_BACKPRESSURE, mask_sh),\
+ SF(WBSCL_CLAMP_Y_RGB, WBSCL_CLAMP_UPPER_Y_RGB, mask_sh),\
+ SF(WBSCL_CLAMP_Y_RGB, WBSCL_CLAMP_LOWER_Y_RGB, mask_sh),\
+ SF(WBSCL_CLAMP_CBCR, WBSCL_CLAMP_UPPER_CBCR, mask_sh),\
+ SF(WBSCL_CLAMP_CBCR, WBSCL_CLAMP_LOWER_CBCR, mask_sh),\
+ SF(WBSCL_OUTSIDE_PIX_STRATEGY, WBSCL_OUTSIDE_PIX_STRATEGY, mask_sh),\
+ SF(WBSCL_OUTSIDE_PIX_STRATEGY, WBSCL_BLACK_COLOR_G_Y, mask_sh),\
+ SF(WBSCL_OUTSIDE_PIX_STRATEGY_CBCR, WBSCL_BLACK_COLOR_B_CB, mask_sh),\
+ SF(WBSCL_OUTSIDE_PIX_STRATEGY_CBCR, WBSCL_BLACK_COLOR_R_CR, mask_sh),\
+ SF(WBSCL_DEBUG, WBSCL_DEBUG, mask_sh),\
+ SF(WBSCL_TEST_DEBUG_INDEX, WBSCL_TEST_DEBUG_INDEX, mask_sh),\
+ SF(WBSCL_TEST_DEBUG_INDEX, WBSCL_TEST_DEBUG_WRITE_EN, mask_sh),\
+ SF(WBSCL_TEST_DEBUG_DATA, WBSCL_TEST_DEBUG_DATA, mask_sh),\
+ SF(WB_WARM_UP_MODE_CTL1, WIDTH_WARMUP, mask_sh),\
+ SF(WB_WARM_UP_MODE_CTL1, HEIGHT_WARMUP, mask_sh),\
+ SF(WB_WARM_UP_MODE_CTL1, GMC_WARM_UP_ENABLE, mask_sh),\
+ SF(WB_WARM_UP_MODE_CTL2, DATA_VALUE_WARMUP, mask_sh),\
+ SF(WB_WARM_UP_MODE_CTL2, MODE_WARMUP, mask_sh),\
+ SF(WB_WARM_UP_MODE_CTL2, DATA_DEPTH_WARMUP, mask_sh)
+
+#define DWBC_REG_FIELD_LIST_DCN2_0(type) \
+ type WB_ENABLE;\
+ type DISPCLK_R_WB_GATE_DIS;\
+ type DISPCLK_G_WB_GATE_DIS;\
+ type DISPCLK_G_WBSCL_GATE_DIS;\
+ type WB_TEST_CLK_SEL;\
+ type WB_LB_LS_DIS;\
+ type WB_LB_SD_DIS;\
+ type WB_LUT_LS_DIS;\
+ type WBSCL_LB_MEM_PWR_MODE_SEL;\
+ type WBSCL_LB_MEM_PWR_DIS;\
+ type WBSCL_LB_MEM_PWR_FORCE;\
+ type WBSCL_LB_MEM_PWR_STATE;\
+ type WB_RAM_PW_SAVE_MODE;\
+ type WBSCL_LUT_MEM_PWR_STATE;\
+ type CNV_OUT_BPC;\
+ type CNV_FRAME_CAPTURE_RATE;\
+ type CNV_WINDOW_CROP_EN;\
+ type CNV_STEREO_TYPE;\
+ type CNV_INTERLACED_MODE;\
+ type CNV_EYE_SELECTION;\
+ type CNV_STEREO_POLARITY;\
+ type CNV_INTERLACED_FIELD_ORDER;\
+ type CNV_STEREO_SPLIT;\
+ type CNV_NEW_CONTENT;\
+ type CNV_FRAME_CAPTURE_EN_CURRENT;\
+ type CNV_FRAME_CAPTURE_EN;\
+ type CNV_WINDOW_START_X;\
+ type CNV_WINDOW_START_Y;\
+ type CNV_WINDOW_WIDTH;\
+ type CNV_WINDOW_HEIGHT;\
+ type CNV_UPDATE_PENDING;\
+ type CNV_UPDATE_TAKEN;\
+ type CNV_UPDATE_LOCK;\
+ type CNV_SOURCE_WIDTH;\
+ type CNV_SOURCE_HEIGHT;\
+ type CNV_TEST_CRC_EN;\
+ type CNV_TEST_CRC_CONT_EN;\
+ type CNV_TEST_CRC_RED_MASK;\
+ type CNV_TEST_CRC_SIG_RED;\
+ type CNV_TEST_CRC_GREEN_MASK;\
+ type CNV_TEST_CRC_SIG_GREEN;\
+ type CNV_TEST_CRC_BLUE_MASK;\
+ type CNV_TEST_CRC_SIG_BLUE;\
+ type WB_DEBUG_EN;\
+ type WB_DEBUG_SEL;\
+ type WB_DBG_MODE_EN;\
+ type WB_DBG_DIN_FMT;\
+ type WB_DBG_36MODE;\
+ type WB_DBG_CMAP;\
+ type WB_DBG_PXLRATE_ERROR;\
+ type WB_DBG_SOURCE_WIDTH;\
+ type WB_HW_DEBUG;\
+ type CNV_TEST_DEBUG_INDEX;\
+ type CNV_TEST_DEBUG_WRITE_EN;\
+ type CNV_TEST_DEBUG_DATA;\
+ type WB_SOFT_RESET;\
+ type WBSCL_COEF_RAM_TAP_PAIR_IDX;\
+ type WBSCL_COEF_RAM_PHASE;\
+ type WBSCL_COEF_RAM_FILTER_TYPE;\
+ type WBSCL_COEF_RAM_SEL;\
+ type WBSCL_COEF_RAM_SEL_CURRENT;\
+ type WBSCL_COEF_RAM_RD_SEL;\
+ type WBSCL_COEF_RAM_EVEN_TAP_COEF;\
+ type WBSCL_COEF_RAM_EVEN_TAP_COEF_EN;\
+ type WBSCL_COEF_RAM_ODD_TAP_COEF;\
+ type WBSCL_COEF_RAM_ODD_TAP_COEF_EN;\
+ type WBSCL_MODE;\
+ type WBSCL_OUT_BIT_DEPTH;\
+ type WBSCL_V_NUM_OF_TAPS_Y_RGB;\
+ type WBSCL_V_NUM_OF_TAPS_CBCR;\
+ type WBSCL_H_NUM_OF_TAPS_Y_RGB;\
+ type WBSCL_H_NUM_OF_TAPS_CBCR;\
+ type WBSCL_DEST_HEIGHT;\
+ type WBSCL_DEST_WIDTH;\
+ type WBSCL_H_SCALE_RATIO;\
+ type WBSCL_H_INIT_FRAC_Y_RGB;\
+ type WBSCL_H_INIT_INT_Y_RGB;\
+ type WBSCL_H_INIT_FRAC_CBCR;\
+ type WBSCL_H_INIT_INT_CBCR;\
+ type WBSCL_V_SCALE_RATIO;\
+ type WBSCL_V_INIT_FRAC_Y_RGB;\
+ type WBSCL_V_INIT_INT_Y_RGB;\
+ type WBSCL_V_INIT_FRAC_CBCR;\
+ type WBSCL_V_INIT_INT_CBCR;\
+ type WBSCL_ROUND_OFFSET_Y_RGB;\
+ type WBSCL_ROUND_OFFSET_CBCR;\
+ type WBSCL_DATA_OVERFLOW_FLAG;\
+ type WBSCL_DATA_OVERFLOW_ACK;\
+ type WBSCL_DATA_OVERFLOW_MASK;\
+ type WBSCL_DATA_OVERFLOW_INT_STATUS;\
+ type WBSCL_DATA_OVERFLOW_INT_TYPE;\
+ type WBSCL_HOST_CONFLICT_FLAG;\
+ type WBSCL_HOST_CONFLICT_ACK;\
+ type WBSCL_HOST_CONFLICT_MASK;\
+ type WBSCL_HOST_CONFLICT_INT_STATUS;\
+ type WBSCL_HOST_CONFLICT_INT_TYPE;\
+ type WBSCL_TEST_CRC_EN;\
+ type WBSCL_TEST_CRC_CONT_EN;\
+ type WBSCL_TEST_CRC_RED_MASK;\
+ type WBSCL_TEST_CRC_SIG_RED;\
+ type WBSCL_TEST_CRC_GREEN_MASK;\
+ type WBSCL_TEST_CRC_SIG_GREEN;\
+ type WBSCL_TEST_CRC_BLUE_MASK;\
+ type WBSCL_TEST_CRC_SIG_BLUE;\
+ type WBSCL_BACKPRESSURE_CNT_EN;\
+ type WB_MCIF_Y_MAX_BACKPRESSURE;\
+ type WB_MCIF_C_MAX_BACKPRESSURE;\
+ type WBSCL_CLAMP_UPPER_Y_RGB;\
+ type WBSCL_CLAMP_LOWER_Y_RGB;\
+ type WBSCL_CLAMP_UPPER_CBCR;\
+ type WBSCL_CLAMP_LOWER_CBCR;\
+ type WBSCL_OUTSIDE_PIX_STRATEGY;\
+ type WBSCL_BLACK_COLOR_G_Y;\
+ type WBSCL_BLACK_COLOR_B_CB;\
+ type WBSCL_BLACK_COLOR_R_CR;\
+ type WBSCL_DEBUG;\
+ type WBSCL_TEST_DEBUG_INDEX;\
+ type WBSCL_TEST_DEBUG_WRITE_EN;\
+ type WBSCL_TEST_DEBUG_DATA;\
+ type WIDTH_WARMUP;\
+ type HEIGHT_WARMUP;\
+ type GMC_WARM_UP_ENABLE;\
+ type DATA_VALUE_WARMUP;\
+ type MODE_WARMUP;\
+ type DATA_DEPTH_WARMUP; \
+
+struct dcn20_dwbc_registers {
+ /* DCN2.0 */
+ uint32_t WB_ENABLE;
+ uint32_t WB_EC_CONFIG;
+ uint32_t CNV_MODE;
+ uint32_t CNV_WINDOW_START;
+ uint32_t CNV_WINDOW_SIZE;
+ uint32_t CNV_UPDATE;
+ uint32_t CNV_SOURCE_SIZE;
+ uint32_t CNV_TEST_CNTL;
+ uint32_t CNV_TEST_CRC_RED;
+ uint32_t CNV_TEST_CRC_GREEN;
+ uint32_t CNV_TEST_CRC_BLUE;
+ uint32_t WB_DEBUG_CTRL;
+ uint32_t WB_DBG_MODE;
+ uint32_t WB_HW_DEBUG;
+ uint32_t CNV_TEST_DEBUG_INDEX;
+ uint32_t CNV_TEST_DEBUG_DATA;
+ uint32_t WB_SOFT_RESET;
+ uint32_t WBSCL_COEF_RAM_SELECT;
+ uint32_t WBSCL_COEF_RAM_TAP_DATA;
+ uint32_t WBSCL_MODE;
+ uint32_t WBSCL_TAP_CONTROL;
+ uint32_t WBSCL_DEST_SIZE;
+ uint32_t WBSCL_HORZ_FILTER_SCALE_RATIO;
+ uint32_t WBSCL_HORZ_FILTER_INIT_Y_RGB;
+ uint32_t WBSCL_HORZ_FILTER_INIT_CBCR;
+ uint32_t WBSCL_VERT_FILTER_SCALE_RATIO;
+ uint32_t WBSCL_VERT_FILTER_INIT_Y_RGB;
+ uint32_t WBSCL_VERT_FILTER_INIT_CBCR;
+ uint32_t WBSCL_ROUND_OFFSET;
+ uint32_t WBSCL_OVERFLOW_STATUS;
+ uint32_t WBSCL_COEF_RAM_CONFLICT_STATUS;
+ uint32_t WBSCL_TEST_CNTL;
+ uint32_t WBSCL_TEST_CRC_RED;
+ uint32_t WBSCL_TEST_CRC_GREEN;
+ uint32_t WBSCL_TEST_CRC_BLUE;
+ uint32_t WBSCL_BACKPRESSURE_CNT_EN;
+ uint32_t WB_MCIF_BACKPRESSURE_CNT;
+ uint32_t WBSCL_CLAMP_Y_RGB;
+ uint32_t WBSCL_CLAMP_CBCR;
+ uint32_t WBSCL_OUTSIDE_PIX_STRATEGY;
+ uint32_t WBSCL_OUTSIDE_PIX_STRATEGY_CBCR;
+ uint32_t WBSCL_DEBUG;
+ uint32_t WBSCL_TEST_DEBUG_INDEX;
+ uint32_t WBSCL_TEST_DEBUG_DATA;
+ uint32_t WB_WARM_UP_MODE_CTL1;
+ uint32_t WB_WARM_UP_MODE_CTL2;
+};
+
+
+struct dcn20_dwbc_mask {
+ DWBC_REG_FIELD_LIST_DCN2_0(uint32_t)
+};
+
+struct dcn20_dwbc_shift {
+ DWBC_REG_FIELD_LIST_DCN2_0(uint8_t)
+};
+
+struct dcn20_dwbc {
+ struct dwbc base;
+ const struct dcn20_dwbc_registers *dwbc_regs;
+ const struct dcn20_dwbc_shift *dwbc_shift;
+ const struct dcn20_dwbc_mask *dwbc_mask;
+};
+
+void dcn20_dwbc_construct(struct dcn20_dwbc *dwbc20,
+ struct dc_context *ctx,
+ const struct dcn20_dwbc_registers *dwbc_regs,
+ const struct dcn20_dwbc_shift *dwbc_shift,
+ const struct dcn20_dwbc_mask *dwbc_mask,
+ int inst);
+
+bool dwb2_disable(struct dwbc *dwbc);
+
+bool dwb2_is_enabled(struct dwbc *dwbc);
+
+void dwb2_set_stereo(struct dwbc *dwbc,
+ struct dwb_stereo_params *stereo_params);
+
+void dwb2_set_new_content(struct dwbc *dwbc,
+ bool is_new_content);
+
+void dwb2_config_dwb_cnv(struct dwbc *dwbc,
+ struct dc_dwb_params *params);
+
+void dwb2_set_scaler(struct dwbc *dwbc, struct dc_dwb_params *params);
+
+bool dwb_program_vert_scalar(struct dcn20_dwbc *dwbc20,
+ uint32_t src_height,
+ uint32_t dest_height,
+ struct scaling_taps num_taps,
+ enum dwb_subsample_position subsample_position);
+
+bool dwb_program_horz_scalar(struct dcn20_dwbc *dwbc20,
+ uint32_t src_width,
+ uint32_t dest_width,
+ struct scaling_taps num_taps);
+
+
+#endif
+
+
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb_scl.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb_scl.c
new file mode 100644
index 000000000000..cd8bc92ce3ba
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb_scl.c
@@ -0,0 +1,877 @@
+/*
+ * Copyright 2012-17 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#include "reg_helper.h"
+#include "fixed31_32.h"
+#include "resource.h"
+#include "dwb.h"
+#include "dcn20_dwb.h"
+
+#define NUM_PHASES 16
+#define HORZ_MAX_TAPS 12
+#define VERT_MAX_TAPS 12
+
+#define REG(reg)\
+ dwbc20->dwbc_regs->reg
+
+#define CTX \
+ dwbc20->base.ctx
+
+#undef FN
+#define FN(reg_name, field_name) \
+ dwbc20->dwbc_shift->field_name, dwbc20->dwbc_mask->field_name
+
+#define TO_DCN20_DWBC(dwbc_base) \
+ container_of(dwbc_base, struct dcn20_dwbc, base)
+
+
+static const uint16_t filter_3tap_16p_upscale[27] = {
+ 2048, 2048, 0,
+ 1708, 2424, 16348,
+ 1372, 2796, 16308,
+ 1056, 3148, 16272,
+ 768, 3464, 16244,
+ 512, 3728, 16236,
+ 296, 3928, 16252,
+ 124, 4052, 16296,
+ 0, 4096, 0
+};
+
+static const uint16_t filter_3tap_16p_117[27] = {
+ 2048, 2048, 0,
+ 1824, 2276, 16376,
+ 1600, 2496, 16380,
+ 1376, 2700, 16,
+ 1156, 2880, 52,
+ 948, 3032, 108,
+ 756, 3144, 192,
+ 580, 3212, 296,
+ 428, 3236, 428
+};
+
+static const uint16_t filter_3tap_16p_150[27] = {
+ 2048, 2048, 0,
+ 1872, 2184, 36,
+ 1692, 2308, 88,
+ 1516, 2420, 156,
+ 1340, 2516, 236,
+ 1168, 2592, 328,
+ 1004, 2648, 440,
+ 844, 2684, 560,
+ 696, 2696, 696
+};
+
+static const uint16_t filter_3tap_16p_183[27] = {
+ 2048, 2048, 0,
+ 1892, 2104, 92,
+ 1744, 2152, 196,
+ 1592, 2196, 300,
+ 1448, 2232, 412,
+ 1304, 2256, 528,
+ 1168, 2276, 648,
+ 1032, 2288, 772,
+ 900, 2292, 900
+};
+
+static const uint16_t filter_4tap_16p_upscale[36] = {
+ 0, 4096, 0, 0,
+ 16240, 4056, 180, 16380,
+ 16136, 3952, 404, 16364,
+ 16072, 3780, 664, 16344,
+ 16040, 3556, 952, 16312,
+ 16036, 3284, 1268, 16272,
+ 16052, 2980, 1604, 16224,
+ 16084, 2648, 1952, 16176,
+ 16128, 2304, 2304, 16128
+};
+
+static const uint16_t filter_4tap_16p_117[36] = {
+ 428, 3236, 428, 0,
+ 276, 3232, 604, 16364,
+ 148, 3184, 800, 16340,
+ 44, 3104, 1016, 16312,
+ 16344, 2984, 1244, 16284,
+ 16284, 2832, 1488, 16256,
+ 16244, 2648, 1732, 16236,
+ 16220, 2440, 1976, 16220,
+ 16212, 2216, 2216, 16212
+};
+
+static const uint16_t filter_4tap_16p_150[36] = {
+ 696, 2700, 696, 0,
+ 560, 2700, 848, 16364,
+ 436, 2676, 1008, 16348,
+ 328, 2628, 1180, 16336,
+ 232, 2556, 1356, 16328,
+ 152, 2460, 1536, 16328,
+ 84, 2344, 1716, 16332,
+ 28, 2208, 1888, 16348,
+ 16376, 2052, 2052, 16376
+};
+
+static const uint16_t filter_4tap_16p_183[36] = {
+ 940, 2208, 940, 0,
+ 832, 2200, 1052, 4,
+ 728, 2180, 1164, 16,
+ 628, 2148, 1280, 36,
+ 536, 2100, 1392, 60,
+ 448, 2044, 1504, 92,
+ 368, 1976, 1612, 132,
+ 296, 1900, 1716, 176,
+ 232, 1812, 1812, 232
+};
+
+static const uint16_t filter_5tap_16p_upscale[45] = {
+ 15936, 2496, 2496, 15936, 0,
+ 15992, 2128, 2832, 15896, 12,
+ 16056, 1760, 3140, 15876, 24,
+ 16120, 1404, 3420, 15876, 36,
+ 16188, 1060, 3652, 15908, 44,
+ 16248, 744, 3844, 15972, 44,
+ 16304, 460, 3980, 16072, 40,
+ 16348, 212, 4064, 16208, 24,
+ 0, 0, 4096, 0, 0,
+};
+
+static const uint16_t filter_5tap_16p_117[45] = {
+ 16056, 2372, 2372, 16056, 0,
+ 16052, 2124, 2600, 16076, 0,
+ 16060, 1868, 2808, 16120, 0,
+ 16080, 1612, 2992, 16180, 16376,
+ 16112, 1356, 3144, 16268, 16364,
+ 16144, 1108, 3268, 16376, 16344,
+ 16184, 872, 3356, 124, 16320,
+ 16220, 656, 3412, 276, 16292,
+ 16256, 456, 3428, 456, 16256,
+};
+
+static const uint16_t filter_5tap_16p_150[45] = {
+ 16368, 2064, 2064, 16368, 0,
+ 16316, 1924, 2204, 44, 16372,
+ 16280, 1772, 2328, 116, 16356,
+ 16256, 1616, 2440, 204, 16340,
+ 16240, 1456, 2536, 304, 16320,
+ 16232, 1296, 2612, 416, 16300,
+ 16232, 1132, 2664, 544, 16284,
+ 16240, 976, 2700, 680, 16264,
+ 16248, 824, 2708, 824, 16248,
+};
+
+static const uint16_t filter_5tap_16p_183[45] = {
+ 228, 1816, 1816, 228, 0,
+ 168, 1728, 1904, 300, 16372,
+ 116, 1632, 1988, 376, 16360,
+ 72, 1528, 2060, 460, 16348,
+ 36, 1424, 2120, 552, 16340,
+ 4, 1312, 2168, 652, 16336,
+ 16368, 1200, 2204, 752, 16332,
+ 16352, 1084, 2224, 860, 16332,
+ 16340, 972, 2232, 972, 16340,
+};
+
+static const uint16_t filter_6tap_16p_upscale[54] = {
+ 0, 0, 4092, 0, 0, 0,
+ 44, 16188, 4064, 228, 16324, 0,
+ 80, 16036, 3980, 492, 16256, 4,
+ 108, 15916, 3844, 788, 16184, 16,
+ 120, 15836, 3656, 1108, 16104, 28,
+ 128, 15792, 3420, 1448, 16024, 44,
+ 124, 15776, 3144, 1800, 15948, 64,
+ 112, 15792, 2836, 2152, 15880, 80,
+ 100, 15828, 2504, 2504, 15828, 100,
+};
+
+static const uint16_t filter_6tap_16p_117[54] = {
+ 16168, 476, 3568, 476, 16168, 0,
+ 16216, 280, 3540, 692, 16116, 8,
+ 16264, 104, 3472, 924, 16068, 16,
+ 16304, 16340, 3372, 1168, 16024, 28,
+ 16344, 16212, 3236, 1424, 15988, 36,
+ 16372, 16112, 3072, 1680, 15956, 44,
+ 12, 16036, 2880, 1936, 15940, 48,
+ 28, 15984, 2668, 2192, 15936, 48,
+ 40, 15952, 2436, 2436, 15952, 40,
+};
+
+static const uint16_t filter_6tap_16p_150[54] = {
+ 16148, 920, 2724, 920, 16148, 0,
+ 16156, 768, 2712, 1072, 16144, 0,
+ 16172, 628, 2684, 1232, 16148, 16380,
+ 16192, 492, 2632, 1388, 16160, 16372,
+ 16212, 368, 2564, 1548, 16180, 16364,
+ 16232, 256, 2480, 1704, 16212, 16352,
+ 16256, 156, 2380, 1856, 16256, 16336,
+ 16276, 64, 2268, 2004, 16308, 16320,
+ 16300, 16372, 2140, 2140, 16372, 16300,
+};
+
+static const uint16_t filter_6tap_16p_183[54] = {
+ 16296, 1032, 2196, 1032, 16296, 0,
+ 16284, 924, 2196, 1144, 16320, 16376,
+ 16272, 820, 2180, 1256, 16348, 16364,
+ 16268, 716, 2156, 1364, 16380, 16352,
+ 16264, 620, 2116, 1472, 36, 16340,
+ 16268, 524, 2068, 1576, 88, 16328,
+ 16272, 436, 2008, 1680, 144, 16316,
+ 16280, 352, 1940, 1772, 204, 16304,
+ 16292, 276, 1860, 1860, 276, 16292,
+};
+
+static const uint16_t filter_7tap_16p_upscale[63] = {
+ 176, 15760, 2488, 2488, 15760, 176, 0,
+ 160, 15812, 2152, 2816, 15728, 192, 16376,
+ 136, 15884, 1812, 3124, 15720, 196, 16368,
+ 108, 15964, 1468, 3400, 15740, 196, 16364,
+ 84, 16048, 1132, 3640, 15792, 180, 16360,
+ 56, 16140, 812, 3832, 15884, 152, 16360,
+ 32, 16228, 512, 3976, 16012, 116, 16364,
+ 12, 16308, 240, 4064, 16180, 60, 16372,
+ 0, 0, 0, 4096, 0, 0, 0,
+};
+
+static const uint16_t filter_7tap_16p_117[63] = {
+ 92, 15868, 2464, 2464, 15868, 92, 0,
+ 108, 15852, 2216, 2700, 15904, 72, 0,
+ 112, 15856, 1960, 2916, 15964, 44, 0,
+ 116, 15876, 1696, 3108, 16048, 8, 8,
+ 112, 15908, 1428, 3268, 16156, 16348, 12,
+ 104, 15952, 1168, 3400, 16288, 16300, 24,
+ 92, 16004, 916, 3496, 64, 16244, 36,
+ 80, 16064, 676, 3556, 248, 16184, 48,
+ 64, 16124, 452, 3576, 452, 16124, 64,
+};
+
+static const uint16_t filter_7tap_16p_150[63] = {
+ 16224, 16380, 2208, 2208, 16380, 16224, 0,
+ 16252, 16304, 2072, 2324, 84, 16196, 4,
+ 16276, 16240, 1924, 2432, 184, 16172, 8,
+ 16300, 16184, 1772, 2524, 296, 16144, 12,
+ 16324, 16144, 1616, 2600, 416, 16124, 12,
+ 16344, 16112, 1456, 2660, 548, 16104, 12,
+ 16360, 16092, 1296, 2704, 688, 16088, 12,
+ 16372, 16080, 1140, 2732, 832, 16080, 8,
+ 0, 16076, 984, 2740, 984, 16076, 0,
+};
+
+static const uint16_t filter_7tap_16p_183[63] = {
+ 16216, 324, 1884, 1884, 324, 16216, 0,
+ 16228, 248, 1804, 1960, 408, 16212, 16380,
+ 16240, 176, 1716, 2028, 496, 16208, 16376,
+ 16252, 112, 1624, 2084, 588, 16208, 16372,
+ 16264, 56, 1524, 2132, 684, 16212, 16364,
+ 16280, 4, 1424, 2168, 788, 16220, 16356,
+ 16292, 16344, 1320, 2196, 892, 16232, 16344,
+ 16308, 16308, 1212, 2212, 996, 16252, 16332,
+ 16320, 16276, 1104, 2216, 1104, 16276, 16320,
+};
+
+static const uint16_t filter_8tap_16p_upscale[72] = {
+ 0, 0, 0, 4096, 0, 0, 0, 0,
+ 16360, 76, 16172, 4064, 244, 16296, 24, 16380,
+ 16340, 136, 15996, 3980, 524, 16204, 56, 16380,
+ 16328, 188, 15860, 3844, 828, 16104, 92, 16372,
+ 16320, 224, 15760, 3656, 1156, 16008, 128, 16368,
+ 16320, 248, 15696, 3428, 1496, 15912, 160, 16360,
+ 16320, 256, 15668, 3156, 1844, 15828, 192, 16348,
+ 16324, 256, 15672, 2856, 2192, 15756, 220, 16340,
+ 16332, 244, 15704, 2532, 2532, 15704, 244, 16332,
+};
+
+static const uint16_t filter_8tap_16p_117[72] = {
+ 116, 16100, 428, 3564, 428, 16100, 116, 0,
+ 96, 16168, 220, 3548, 656, 16032, 136, 16376,
+ 76, 16236, 32, 3496, 904, 15968, 152, 16372,
+ 56, 16300, 16252, 3408, 1164, 15908, 164, 16368,
+ 36, 16360, 16116, 3284, 1428, 15856, 172, 16364,
+ 20, 28, 16000, 3124, 1700, 15820, 176, 16364,
+ 4, 76, 15912, 2940, 1972, 15800, 172, 16364,
+ 16380, 112, 15848, 2724, 2236, 15792, 160, 16364,
+ 16372, 140, 15812, 2488, 2488, 15812, 140, 16372,
+};
+
+static const uint16_t filter_8tap_16p_150[72] = {
+ 16380, 16020, 1032, 2756, 1032, 16020, 16380, 0,
+ 12, 16020, 876, 2744, 1184, 16032, 16364, 4,
+ 24, 16028, 728, 2716, 1344, 16052, 16340, 8,
+ 36, 16040, 584, 2668, 1500, 16080, 16316, 16,
+ 40, 16060, 448, 2608, 1652, 16120, 16288, 20,
+ 44, 16080, 320, 2528, 1804, 16168, 16260, 28,
+ 48, 16108, 204, 2436, 1948, 16232, 16228, 32,
+ 44, 16136, 100, 2328, 2084, 16304, 16200, 40,
+ 44, 16168, 4, 2212, 2212, 4, 16168, 44,
+};
+
+static const uint16_t filter_8tap_16p_183[72] = {
+ 16264, 16264, 1164, 2244, 1164, 16264, 16264, 0,
+ 16280, 16232, 1056, 2236, 1268, 16300, 16248, 0,
+ 16296, 16204, 948, 2220, 1372, 16348, 16232, 0,
+ 16312, 16184, 844, 2192, 1472, 12, 16216, 4,
+ 16328, 16172, 740, 2156, 1572, 72, 16200, 0,
+ 16340, 16160, 640, 2108, 1668, 136, 16188, 0,
+ 16352, 16156, 544, 2052, 1756, 204, 16176, 16380,
+ 16360, 16156, 452, 1988, 1840, 280, 16164, 16376,
+ 16368, 16160, 364, 1920, 1920, 364, 16160, 16368,
+};
+
+static const uint16_t filter_9tap_16p_upscale[81] = {
+ 16284, 296, 15660, 2572, 2572, 15660, 296, 16284, 0,
+ 16296, 272, 15712, 2228, 2896, 15632, 304, 16276, 4,
+ 16308, 240, 15788, 1876, 3192, 15632, 304, 16276, 4,
+ 16320, 204, 15876, 1520, 3452, 15664, 288, 16280, 8,
+ 16336, 164, 15976, 1176, 3676, 15732, 260, 16288, 12,
+ 16348, 120, 16080, 844, 3856, 15840, 216, 16300, 12,
+ 16364, 76, 16188, 532, 3988, 15984, 156, 16324, 8,
+ 16376, 36, 16288, 252, 4068, 16164, 84, 16352, 4,
+ 0, 0, 0, 0, 4096, 0, 0, 0, 0,
+};
+
+static const uint16_t filter_9tap_16p_117[81] = {
+ 16356, 172, 15776, 2504, 2504, 15776, 172, 16356, 0,
+ 16344, 200, 15756, 2252, 2740, 15816, 136, 16372, 16380,
+ 16336, 216, 15756, 1988, 2956, 15884, 92, 8, 16380,
+ 16332, 224, 15780, 1720, 3144, 15976, 40, 28, 16376,
+ 16328, 224, 15816, 1448, 3304, 16096, 16364, 52, 16372,
+ 16328, 216, 15868, 1180, 3432, 16240, 16296, 80, 16364,
+ 16332, 200, 15928, 916, 3524, 24, 16224, 108, 16356,
+ 16336, 184, 15996, 668, 3580, 220, 16148, 132, 16352,
+ 16344, 160, 16072, 436, 3600, 436, 16072, 160, 16344,
+};
+
+static const uint16_t filter_9tap_16p_150[81] = {
+ 84, 16128, 0, 2216, 2216, 0, 16128, 84, 0,
+ 80, 16160, 16296, 2088, 2332, 100, 16092, 84, 0,
+ 76, 16196, 16220, 1956, 2432, 208, 16064, 80, 0,
+ 72, 16232, 16152, 1812, 2524, 328, 16036, 76, 4,
+ 64, 16264, 16096, 1664, 2600, 460, 16012, 64, 8,
+ 56, 16300, 16052, 1508, 2656, 596, 15996, 52, 12,
+ 48, 16328, 16020, 1356, 2700, 740, 15984, 36, 20,
+ 40, 16356, 15996, 1196, 2728, 888, 15980, 20, 24,
+ 32, 0, 15984, 1044, 2736, 1044, 15984, 0, 32,
+};
+
+static const uint16_t filter_9tap_16p_183[81] = {
+ 16356, 16112, 388, 1952, 1952, 388, 16112, 16356, 0,
+ 16368, 16116, 304, 1876, 2020, 480, 16112, 16344, 4,
+ 16376, 16124, 224, 1792, 2080, 576, 16116, 16328, 8,
+ 0, 16136, 148, 1700, 2132, 672, 16124, 16312, 8,
+ 8, 16148, 80, 1604, 2176, 772, 16140, 16296, 12,
+ 12, 16164, 16, 1504, 2208, 876, 16156, 16276, 16,
+ 16, 16180, 16344, 1404, 2232, 980, 16184, 16256, 20,
+ 20, 16200, 16296, 1300, 2244, 1088, 16212, 16240, 20,
+ 20, 16220, 16252, 1196, 2252, 1196, 16252, 16220, 20,
+};
+
+static const uint16_t filter_10tap_16p_upscale[90] = {
+ 0, 0, 0, 0, 4096, 0, 0, 0, 0, 0,
+ 12, 16344, 88, 16160, 4068, 252, 16280, 44, 16368, 0,
+ 24, 16308, 168, 15976, 3988, 540, 16176, 92, 16348, 0,
+ 32, 16280, 236, 15828, 3852, 852, 16064, 140, 16328, 4,
+ 36, 16260, 284, 15720, 3672, 1184, 15956, 188, 16308, 8,
+ 36, 16244, 320, 15648, 3448, 1528, 15852, 236, 16288, 12,
+ 36, 16240, 336, 15612, 3184, 1880, 15764, 276, 16272, 20,
+ 32, 16240, 340, 15608, 2888, 2228, 15688, 308, 16256, 24,
+ 28, 16244, 332, 15636, 2568, 2568, 15636, 332, 16244, 28,
+};
+
+static const uint16_t filter_10tap_16p_117[90] = {
+ 16308, 196, 16048, 440, 3636, 440, 16048, 196, 16308, 0,
+ 16316, 164, 16132, 220, 3612, 676, 15972, 220, 16300, 0,
+ 16324, 132, 16212, 20, 3552, 932, 15900, 240, 16296, 4,
+ 16336, 100, 16292, 16232, 3456, 1192, 15836, 256, 16296, 4,
+ 16348, 68, 16364, 16084, 3324, 1464, 15784, 264, 16296, 8,
+ 16356, 36, 48, 15960, 3164, 1736, 15748, 260, 16304, 4,
+ 16364, 8, 108, 15864, 2972, 2008, 15728, 252, 16312, 4,
+ 16372, 16368, 160, 15792, 2756, 2268, 15724, 228, 16328, 0,
+ 16380, 16344, 200, 15748, 2520, 2520, 15748, 200, 16344, 16380,
+};
+
+static const uint16_t filter_10tap_16p_150[90] = {
+ 64, 0, 15956, 1048, 2716, 1048, 15956, 0, 64, 0,
+ 52, 24, 15952, 896, 2708, 1204, 15972, 16356, 72, 16380,
+ 44, 48, 15952, 748, 2684, 1360, 16000, 16320, 84, 16380,
+ 32, 68, 15964, 604, 2644, 1516, 16032, 16288, 92, 16376,
+ 24, 88, 15980, 464, 2588, 1668, 16080, 16248, 100, 16376,
+ 16, 100, 16004, 332, 2516, 1816, 16140, 16212, 108, 16376,
+ 8, 108, 16032, 212, 2428, 1956, 16208, 16172, 112, 16376,
+ 4, 116, 16060, 100, 2328, 2092, 16288, 16132, 116, 16380,
+ 0, 116, 16096, 16380, 2216, 2216, 16380, 16096, 116, 0,
+};
+
+static const uint16_t filter_10tap_16p_183[90] = {
+ 40, 16180, 16240, 1216, 2256, 1216, 16240, 16180, 40, 0,
+ 44, 16204, 16200, 1112, 2252, 1320, 16288, 16160, 36, 0,
+ 44, 16224, 16168, 1004, 2236, 1424, 16344, 16144, 28, 4,
+ 44, 16248, 16136, 900, 2208, 1524, 16, 16124, 24, 8,
+ 44, 16268, 16116, 796, 2176, 1620, 84, 16108, 12, 12,
+ 40, 16288, 16100, 692, 2132, 1712, 156, 16096, 4, 16,
+ 36, 16308, 16088, 592, 2080, 1796, 232, 16088, 16376, 20,
+ 32, 16328, 16080, 496, 2020, 1876, 316, 16080, 16360, 24,
+ 28, 16344, 16080, 404, 1952, 1952, 404, 16080, 16344, 28,
+};
+
+static const uint16_t filter_11tap_16p_upscale[99] = {
+ 60, 16216, 356, 15620, 2556, 2556, 15620, 356, 16216, 60, 0,
+ 52, 16224, 336, 15672, 2224, 2876, 15592, 368, 16208, 64, 16380,
+ 44, 16244, 304, 15744, 1876, 3176, 15596, 364, 16212, 64, 16376,
+ 36, 16264, 260, 15836, 1532, 3440, 15636, 340, 16220, 60, 16376,
+ 28, 16288, 212, 15940, 1188, 3668, 15708, 304, 16236, 56, 16376,
+ 20, 16312, 160, 16052, 856, 3848, 15820, 248, 16264, 48, 16376,
+ 12, 16336, 104, 16164, 544, 3984, 15968, 180, 16296, 36, 16376,
+ 4, 16360, 48, 16276, 256, 4068, 16160, 96, 16336, 16, 16380,
+ 0, 0, 0, 0, 0, 4096, 0, 0, 0, 0, 0,
+};
+
+static const uint16_t filter_11tap_16p_117[99] = {
+ 16380, 16332, 220, 15728, 2536, 2536, 15728, 220, 16332, 16380, 0,
+ 4, 16308, 256, 15704, 2280, 2768, 15772, 176, 16360, 16368, 0,
+ 12, 16292, 280, 15704, 2016, 2984, 15848, 120, 8, 16356, 0,
+ 20, 16276, 292, 15724, 1744, 3172, 15948, 56, 40, 16340, 4,
+ 24, 16268, 292, 15760, 1468, 3328, 16072, 16368, 80, 16324, 8,
+ 24, 16264, 288, 15816, 1196, 3456, 16224, 16288, 116, 16312, 12,
+ 24, 16264, 272, 15880, 932, 3548, 16, 16208, 152, 16296, 16,
+ 24, 16268, 248, 15956, 676, 3604, 216, 16120, 188, 16284, 20,
+ 24, 16276, 220, 16036, 436, 3624, 436, 16036, 220, 16276, 24,
+};
+
+static const uint16_t filter_11tap_16p_150[99] = {
+ 0, 144, 16072, 0, 2212, 2212, 0, 16072, 144, 0, 0,
+ 16376, 144, 16112, 16288, 2092, 2324, 104, 16036, 140, 8, 16380,
+ 16368, 144, 16152, 16204, 1960, 2424, 216, 16004, 132, 16, 16376,
+ 16364, 140, 16192, 16132, 1820, 2512, 340, 15976, 116, 28, 16376,
+ 16364, 132, 16232, 16072, 1676, 2584, 476, 15952, 100, 40, 16372,
+ 16360, 124, 16272, 16020, 1528, 2644, 612, 15936, 80, 52, 16368,
+ 16360, 116, 16312, 15980, 1372, 2684, 760, 15928, 56, 64, 16364,
+ 16360, 104, 16348, 15952, 1216, 2712, 908, 15928, 28, 76, 16364,
+ 16360, 92, 0, 15936, 1064, 2720, 1064, 15936, 0, 92, 16360,
+};
+
+static const uint16_t filter_11tap_16p_183[99] = {
+ 60, 16336, 16052, 412, 1948, 1948, 412, 16052, 16336, 60, 0,
+ 56, 16356, 16052, 324, 1876, 2016, 504, 16056, 16316, 64, 0,
+ 48, 16372, 16060, 240, 1796, 2072, 604, 16064, 16292, 64, 0,
+ 44, 4, 16068, 160, 1712, 2124, 700, 16080, 16272, 68, 0,
+ 40, 20, 16080, 84, 1620, 2164, 804, 16096, 16248, 68, 4,
+ 32, 32, 16096, 16, 1524, 2200, 908, 16124, 16224, 68, 4,
+ 28, 40, 16112, 16340, 1428, 2220, 1012, 16152, 16200, 64, 8,
+ 24, 52, 16132, 16284, 1328, 2236, 1120, 16192, 16176, 64, 12,
+ 16, 56, 16156, 16236, 1224, 2240, 1224, 16236, 16156, 56, 16,
+};
+
+static const uint16_t filter_12tap_16p_upscale[108] = {
+ 0, 0, 0, 0, 0, 4096, 0, 0, 0, 0, 0, 0,
+ 16376, 24, 16332, 100, 16156, 4068, 260, 16272, 56, 16356, 8, 0,
+ 16368, 44, 16284, 188, 15964, 3988, 548, 16156, 112, 16328, 20, 16380,
+ 16360, 64, 16248, 260, 15812, 3856, 864, 16040, 172, 16296, 32, 16380,
+ 16360, 76, 16216, 320, 15696, 3672, 1196, 15928, 228, 16268, 44, 16376,
+ 16356, 84, 16196, 360, 15620, 3448, 1540, 15820, 280, 16240, 56, 16372,
+ 16356, 88, 16184, 384, 15580, 3188, 1888, 15728, 324, 16216, 68, 16368,
+ 16360, 88, 16180, 392, 15576, 2892, 2236, 15652, 360, 16200, 80, 16364,
+ 16360, 84, 16188, 384, 15600, 2576, 2576, 15600, 384, 16188, 84, 16360,
+};
+
+static const uint16_t filter_12tap_16p_117[108] = {
+ 48, 16248, 240, 16028, 436, 3612, 436, 16028, 240, 16248, 48, 0,
+ 44, 16260, 208, 16116, 212, 3596, 676, 15944, 272, 16240, 48, 16380,
+ 40, 16276, 168, 16204, 12, 3540, 932, 15868, 296, 16240, 48, 16380,
+ 36, 16292, 128, 16288, 16220, 3452, 1196, 15800, 312, 16240, 44, 16380,
+ 28, 16308, 84, 16372, 16064, 3324, 1472, 15748, 316, 16244, 40, 16380,
+ 24, 16328, 44, 64, 15936, 3168, 1744, 15708, 312, 16256, 32, 16380,
+ 16, 16344, 8, 132, 15836, 2980, 2016, 15688, 300, 16272, 20, 0,
+ 12, 16364, 16356, 188, 15760, 2768, 2280, 15688, 272, 16296, 8, 4,
+ 8, 16380, 16324, 236, 15712, 2532, 2532, 15712, 236, 16324, 16380, 8,
+};
+
+static const uint16_t filter_12tap_16p_150[108] = {
+ 16340, 116, 0, 15916, 1076, 2724, 1076, 15916, 0, 116, 16340, 0,
+ 16340, 100, 32, 15908, 920, 2716, 1232, 15936, 16344, 128, 16340, 0,
+ 16344, 84, 64, 15908, 772, 2692, 1388, 15968, 16304, 140, 16344, 16380,
+ 16344, 68, 92, 15912, 624, 2652, 1540, 16008, 16264, 152, 16344, 16380,
+ 16348, 52, 112, 15928, 484, 2592, 1688, 16060, 16220, 160, 16348, 16380,
+ 16352, 40, 132, 15952, 348, 2520, 1836, 16124, 16176, 168, 16356, 16376,
+ 16356, 24, 148, 15980, 224, 2436, 1976, 16200, 16132, 172, 16364, 16372,
+ 16360, 12, 160, 16012, 108, 2336, 2104, 16288, 16088, 172, 16372, 16368,
+ 16364, 0, 168, 16048, 0, 2228, 2228, 0, 16048, 168, 0, 16364,
+};
+
+static const uint16_t filter_12tap_16p_183[108] = {
+ 36, 72, 16132, 16228, 1224, 2224, 1224, 16228, 16132, 72, 36, 0,
+ 28, 80, 16156, 16184, 1120, 2224, 1328, 16280, 16112, 64, 40, 16380,
+ 24, 84, 16180, 16144, 1016, 2208, 1428, 16340, 16092, 52, 48, 16380,
+ 16, 88, 16208, 16112, 912, 2188, 1524, 16, 16072, 36, 56, 16380,
+ 12, 92, 16232, 16084, 812, 2156, 1620, 88, 16056, 24, 64, 16380,
+ 8, 92, 16256, 16064, 708, 2116, 1708, 164, 16044, 4, 68, 16380,
+ 4, 88, 16280, 16048, 608, 2068, 1792, 244, 16036, 16372, 76, 16380,
+ 0, 88, 16308, 16036, 512, 2008, 1872, 328, 16032, 16352, 80, 16380,
+ 0, 84, 16328, 16032, 416, 1944, 1944, 416, 16032, 16328, 84, 0,
+};
+
+const uint16_t *wbscl_get_filter_3tap_16p(struct fixed31_32 ratio)
+{
+ if (ratio.value < dc_fixpt_one.value)
+ return filter_3tap_16p_upscale;
+ else if (ratio.value < dc_fixpt_from_fraction(4, 3).value)
+ return filter_3tap_16p_117;
+ else if (ratio.value < dc_fixpt_from_fraction(5, 3).value)
+ return filter_3tap_16p_150;
+ else
+ return filter_3tap_16p_183;
+}
+
+const uint16_t *wbscl_get_filter_4tap_16p(struct fixed31_32 ratio)
+{
+ if (ratio.value < dc_fixpt_one.value)
+ return filter_4tap_16p_upscale;
+ else if (ratio.value < dc_fixpt_from_fraction(4, 3).value)
+ return filter_4tap_16p_117;
+ else if (ratio.value < dc_fixpt_from_fraction(5, 3).value)
+ return filter_4tap_16p_150;
+ else
+ return filter_4tap_16p_183;
+}
+
+static const uint16_t *wbscl_get_filter_5tap_16p(struct fixed31_32 ratio)
+{
+ if (ratio.value < dc_fixpt_one.value)
+ return filter_5tap_16p_upscale;
+ else if (ratio.value < dc_fixpt_from_fraction(4, 3).value)
+ return filter_5tap_16p_117;
+ else if (ratio.value < dc_fixpt_from_fraction(5, 3).value)
+ return filter_5tap_16p_150;
+ else
+ return filter_5tap_16p_183;
+}
+
+static const uint16_t *wbscl_get_filter_6tap_16p(struct fixed31_32 ratio)
+{
+ if (ratio.value < dc_fixpt_one.value)
+ return filter_6tap_16p_upscale;
+ else if (ratio.value < dc_fixpt_from_fraction(4, 3).value)
+ return filter_6tap_16p_117;
+ else if (ratio.value < dc_fixpt_from_fraction(5, 3).value)
+ return filter_6tap_16p_150;
+ else
+ return filter_6tap_16p_183;
+}
+
+static const uint16_t *wbscl_get_filter_7tap_16p(struct fixed31_32 ratio)
+{
+ if (ratio.value < dc_fixpt_one.value)
+ return filter_7tap_16p_upscale;
+ else if (ratio.value < dc_fixpt_from_fraction(4, 3).value)
+ return filter_7tap_16p_117;
+ else if (ratio.value < dc_fixpt_from_fraction(5, 3).value)
+ return filter_7tap_16p_150;
+ else
+ return filter_7tap_16p_183;
+}
+
+static const uint16_t *wbscl_get_filter_8tap_16p(struct fixed31_32 ratio)
+{
+ if (ratio.value < dc_fixpt_one.value)
+ return filter_8tap_16p_upscale;
+ else if (ratio.value < dc_fixpt_from_fraction(4, 3).value)
+ return filter_8tap_16p_117;
+ else if (ratio.value < dc_fixpt_from_fraction(5, 3).value)
+ return filter_8tap_16p_150;
+ else
+ return filter_8tap_16p_183;
+}
+
+static const uint16_t *wbscl_get_filter_9tap_16p(struct fixed31_32 ratio)
+{
+ if (ratio.value < dc_fixpt_one.value)
+ return filter_9tap_16p_upscale;
+ else if (ratio.value < dc_fixpt_from_fraction(4, 3).value)
+ return filter_9tap_16p_117;
+ else if (ratio.value < dc_fixpt_from_fraction(5, 3).value)
+ return filter_9tap_16p_150;
+ else
+ return filter_9tap_16p_183;
+}
+static const uint16_t *wbscl_get_filter_10tap_16p(struct fixed31_32 ratio)
+{
+ if (ratio.value < dc_fixpt_one.value)
+ return filter_10tap_16p_upscale;
+ else if (ratio.value < dc_fixpt_from_fraction(4, 3).value)
+ return filter_10tap_16p_117;
+ else if (ratio.value < dc_fixpt_from_fraction(5, 3).value)
+ return filter_10tap_16p_150;
+ else
+ return filter_10tap_16p_183;
+}
+
+static const uint16_t *wbscl_get_filter_11tap_16p(struct fixed31_32 ratio)
+{
+ if (ratio.value < dc_fixpt_one.value)
+ return filter_11tap_16p_upscale;
+ else if (ratio.value < dc_fixpt_from_fraction(4, 3).value)
+ return filter_11tap_16p_117;
+ else if (ratio.value < dc_fixpt_from_fraction(5, 3).value)
+ return filter_11tap_16p_150;
+ else
+ return filter_11tap_16p_183;
+}
+
+static const uint16_t *wbscl_get_filter_12tap_16p(struct fixed31_32 ratio)
+{
+ if (ratio.value < dc_fixpt_one.value)
+ return filter_12tap_16p_upscale;
+ else if (ratio.value < dc_fixpt_from_fraction(4, 3).value)
+ return filter_12tap_16p_117;
+ else if (ratio.value < dc_fixpt_from_fraction(5, 3).value)
+ return filter_12tap_16p_150;
+ else
+ return filter_12tap_16p_183;
+}
+
+static const uint16_t *wbscl_get_filter_coeffs_16p(int taps, struct fixed31_32 ratio)
+{
+ if (taps == 12)
+ return wbscl_get_filter_12tap_16p(ratio);
+ else if (taps == 11)
+ return wbscl_get_filter_11tap_16p(ratio);
+ else if (taps == 10)
+ return wbscl_get_filter_10tap_16p(ratio);
+ else if (taps == 9)
+ return wbscl_get_filter_9tap_16p(ratio);
+ else if (taps == 8)
+ return wbscl_get_filter_8tap_16p(ratio);
+ else if (taps == 7)
+ return wbscl_get_filter_7tap_16p(ratio);
+ else if (taps == 6)
+ return wbscl_get_filter_6tap_16p(ratio);
+ else if (taps == 5)
+ return wbscl_get_filter_5tap_16p(ratio);
+ else if (taps == 4)
+ return wbscl_get_filter_4tap_16p(ratio);
+ else if (taps == 3)
+ return wbscl_get_filter_3tap_16p(ratio);
+ else if (taps == 2)
+ return get_filter_2tap_16p();
+ else if (taps == 1)
+ return NULL;
+ else {
+ /* should never happen, bug */
+ BREAK_TO_DEBUGGER();
+ return NULL;
+ }
+}
+
+static void wbscl_set_scaler_filter(
+ struct dcn20_dwbc *dwbc20,
+ uint32_t taps,
+ enum wbscl_coef_filter_type_sel filter_type,
+ const uint16_t *filter)
+{
+ const int tap_pairs = (taps + 1) / 2;
+ int phase;
+ int pair;
+ uint16_t odd_coef, even_coef;
+
+ for (phase = 0; phase < (NUM_PHASES / 2 + 1); phase++) {
+ for (pair = 0; pair < tap_pairs; pair++) {
+ even_coef = filter[phase * taps + 2 * pair];
+ if ((pair * 2 + 1) < taps)
+ odd_coef = filter[phase * taps + 2 * pair + 1];
+ else
+ odd_coef = 0;
+
+ REG_SET_3(WBSCL_COEF_RAM_SELECT, 0,
+ WBSCL_COEF_RAM_TAP_PAIR_IDX, pair,
+ WBSCL_COEF_RAM_PHASE, phase,
+ WBSCL_COEF_RAM_FILTER_TYPE, filter_type);
+
+ REG_SET_4(WBSCL_COEF_RAM_TAP_DATA, 0,
+ /* Even tap coefficient (bits 1:0 fixed to 0) */
+ WBSCL_COEF_RAM_EVEN_TAP_COEF, even_coef,
+ /* Write/read control for even coefficient */
+ WBSCL_COEF_RAM_EVEN_TAP_COEF_EN, 1,
+ /* Odd tap coefficient (bits 1:0 fixed to 0) */
+ WBSCL_COEF_RAM_ODD_TAP_COEF, odd_coef,
+ /* Write/read control for odd coefficient */
+ WBSCL_COEF_RAM_ODD_TAP_COEF_EN, 1);
+ }
+ }
+}
+
+bool dwb_program_horz_scalar(struct dcn20_dwbc *dwbc20,
+ uint32_t src_width,
+ uint32_t dest_width,
+ struct scaling_taps num_taps)
+{
+ uint32_t h_ratio_luma = 1;
+ uint32_t h_ratio_chroma = 1;
+ uint32_t h_taps_luma = num_taps.h_taps;
+ uint32_t h_taps_chroma = num_taps.h_taps_c;
+ int32_t h_init_phase_luma = 0;
+ int32_t h_init_phase_chroma = 0;
+ uint32_t h_init_phase_luma_int = 0;
+ uint32_t h_init_phase_luma_frac = 0;
+ uint32_t h_init_phase_chroma_int = 0;
+ uint32_t h_init_phase_chroma_frac = 0;
+ const uint16_t *filter_h = NULL;
+ const uint16_t *filter_h_c = NULL;
+
+
+ struct fixed31_32 tmp_h_init_phase_luma = dc_fixpt_from_int(0);
+ struct fixed31_32 tmp_h_init_phase_chroma = dc_fixpt_from_int(0);
+
+
+ /*Calculate ratio*/
+ struct fixed31_32 tmp_h_ratio_luma = dc_fixpt_from_fraction(
+ src_width, dest_width);
+
+ if (dc_fixpt_floor(tmp_h_ratio_luma) == 8)
+ h_ratio_luma = -1;
+ else
+ h_ratio_luma = dc_fixpt_u3d19(tmp_h_ratio_luma) << 5;
+ h_ratio_chroma = h_ratio_luma * 2;
+
+ /*Program ratio*/
+ REG_UPDATE(WBSCL_HORZ_FILTER_SCALE_RATIO, WBSCL_H_SCALE_RATIO, h_ratio_luma);
+
+ /* Program taps*/
+ REG_UPDATE(WBSCL_TAP_CONTROL, WBSCL_H_NUM_OF_TAPS_Y_RGB, h_taps_luma - 1);
+ REG_UPDATE(WBSCL_TAP_CONTROL, WBSCL_H_NUM_OF_TAPS_CBCR, h_taps_chroma - 1);
+
+ /* Calculate phase*/
+ tmp_h_init_phase_luma = dc_fixpt_add_int(tmp_h_ratio_luma, h_taps_luma + 1);
+ tmp_h_init_phase_luma = dc_fixpt_div_int(tmp_h_init_phase_luma, 2);
+ tmp_h_init_phase_luma = dc_fixpt_sub_int(tmp_h_init_phase_luma, h_taps_luma);
+
+ h_init_phase_luma = dc_fixpt_s4d19(tmp_h_init_phase_luma);
+ h_init_phase_luma_int = (h_init_phase_luma >> 19) & 0x1f;
+ h_init_phase_luma_frac = (h_init_phase_luma & 0x7ffff) << 5;
+
+ tmp_h_init_phase_chroma = dc_fixpt_mul_int(tmp_h_ratio_luma, 2);
+ tmp_h_init_phase_chroma = dc_fixpt_add_int(tmp_h_init_phase_chroma, h_taps_chroma + 1);
+ tmp_h_init_phase_chroma = dc_fixpt_div_int(tmp_h_init_phase_chroma, 2);
+ tmp_h_init_phase_chroma = dc_fixpt_sub_int(tmp_h_init_phase_chroma, h_taps_chroma);
+ tmp_h_init_phase_chroma = dc_fixpt_add(tmp_h_init_phase_chroma, dc_fixpt_from_fraction(1, 4));
+
+ h_init_phase_chroma = dc_fixpt_s4d19(tmp_h_init_phase_chroma);
+ h_init_phase_chroma_int = (h_init_phase_chroma >> 19) & 0x1f;
+ h_init_phase_chroma_frac = (h_init_phase_chroma & 0x7ffff) << 5;
+
+ /* Program phase*/
+ REG_UPDATE(WBSCL_HORZ_FILTER_INIT_Y_RGB, WBSCL_H_INIT_INT_Y_RGB, h_init_phase_luma_int);
+ REG_UPDATE(WBSCL_HORZ_FILTER_INIT_Y_RGB, WBSCL_H_INIT_FRAC_Y_RGB, h_init_phase_luma_frac);
+ REG_UPDATE(WBSCL_HORZ_FILTER_INIT_CBCR, WBSCL_H_INIT_INT_CBCR, h_init_phase_chroma_int);
+ REG_UPDATE(WBSCL_HORZ_FILTER_INIT_CBCR, WBSCL_H_INIT_FRAC_CBCR, h_init_phase_chroma_frac);
+
+ /* Program LUT coefficients*/
+ filter_h = wbscl_get_filter_coeffs_16p(
+ h_taps_luma, tmp_h_ratio_luma);
+ filter_h_c = wbscl_get_filter_coeffs_16p(
+ h_taps_chroma, dc_fixpt_from_int(h_ratio_luma * 2));
+
+ wbscl_set_scaler_filter(dwbc20, h_taps_luma,
+ WBSCL_COEF_LUMA_HORZ_FILTER, filter_h);
+
+ wbscl_set_scaler_filter(dwbc20, h_taps_chroma,
+ WBSCL_COEF_CHROMA_HORZ_FILTER, filter_h_c);
+
+ return true;
+}
+
+bool dwb_program_vert_scalar(struct dcn20_dwbc *dwbc20,
+ uint32_t src_height,
+ uint32_t dest_height,
+ struct scaling_taps num_taps,
+ enum dwb_subsample_position subsample_position)
+{
+ uint32_t v_ratio_luma = 1;
+ uint32_t v_ratio_chroma = 1;
+ uint32_t v_taps_luma = num_taps.v_taps;
+ uint32_t v_taps_chroma = num_taps.v_taps_c;
+ int32_t v_init_phase_luma = 0;
+ int32_t v_init_phase_chroma = 0;
+ uint32_t v_init_phase_luma_int = 0;
+ uint32_t v_init_phase_luma_frac = 0;
+ uint32_t v_init_phase_chroma_int = 0;
+ uint32_t v_init_phase_chroma_frac = 0;
+
+ const uint16_t *filter_v = NULL;
+ const uint16_t *filter_v_c = NULL;
+
+ struct fixed31_32 tmp_v_init_phase_luma = dc_fixpt_from_int(0);
+ struct fixed31_32 tmp_v_init_phase_chroma = dc_fixpt_from_int(0);
+
+ /*Calculate ratio*/
+ struct fixed31_32 tmp_v_ratio_luma = dc_fixpt_from_fraction(
+ src_height, dest_height);
+
+ if (dc_fixpt_floor(tmp_v_ratio_luma) == 8)
+ v_ratio_luma = -1;
+ else
+ v_ratio_luma = dc_fixpt_u3d19(tmp_v_ratio_luma) << 5;
+ v_ratio_chroma = v_ratio_luma * 2;
+
+ /*Program ratio*/
+ REG_UPDATE(WBSCL_VERT_FILTER_SCALE_RATIO, WBSCL_V_SCALE_RATIO, v_ratio_luma);
+
+ /* Program taps*/
+ REG_UPDATE(WBSCL_TAP_CONTROL, WBSCL_V_NUM_OF_TAPS_Y_RGB, v_taps_luma - 1);
+ REG_UPDATE(WBSCL_TAP_CONTROL, WBSCL_V_NUM_OF_TAPS_CBCR, v_taps_chroma - 1);
+
+ /* Calculate phase*/
+ tmp_v_init_phase_luma = dc_fixpt_add_int(tmp_v_ratio_luma, v_taps_luma + 1);
+ tmp_v_init_phase_luma = dc_fixpt_div_int(tmp_v_init_phase_luma, 2);
+ tmp_v_init_phase_luma = dc_fixpt_sub_int(tmp_v_init_phase_luma, v_taps_luma);
+
+ v_init_phase_luma = dc_fixpt_s4d19(tmp_v_init_phase_luma);
+ v_init_phase_luma_int = (v_init_phase_luma >> 19) & 0x1f;
+ v_init_phase_luma_frac = (v_init_phase_luma & 0x7ffff) << 5;
+
+ tmp_v_init_phase_chroma = dc_fixpt_mul_int(tmp_v_ratio_luma, 2);
+ tmp_v_init_phase_chroma = dc_fixpt_add_int(tmp_v_init_phase_chroma, v_taps_chroma + 1);
+ tmp_v_init_phase_chroma = dc_fixpt_div_int(tmp_v_init_phase_chroma, 2);
+ tmp_v_init_phase_chroma = dc_fixpt_sub_int(tmp_v_init_phase_chroma, v_taps_chroma);
+ if (subsample_position == DWB_COSITED_SUBSAMPLING)
+ tmp_v_init_phase_chroma = dc_fixpt_add(tmp_v_init_phase_chroma, dc_fixpt_from_fraction(1, 4));
+
+ v_init_phase_chroma = dc_fixpt_s4d19(tmp_v_init_phase_chroma);
+ v_init_phase_chroma_int = (v_init_phase_chroma >> 19) & 0x1f;
+ v_init_phase_chroma_frac = (v_init_phase_chroma & 0x7ffff) << 5;
+
+ /* Program phase*/
+ REG_UPDATE(WBSCL_VERT_FILTER_INIT_Y_RGB, WBSCL_V_INIT_INT_Y_RGB, v_init_phase_luma_int);
+ REG_UPDATE(WBSCL_VERT_FILTER_INIT_Y_RGB, WBSCL_V_INIT_FRAC_Y_RGB, v_init_phase_luma_frac);
+ REG_UPDATE(WBSCL_VERT_FILTER_INIT_CBCR, WBSCL_V_INIT_INT_CBCR, v_init_phase_chroma_int);
+ REG_UPDATE(WBSCL_VERT_FILTER_INIT_CBCR, WBSCL_V_INIT_FRAC_CBCR, v_init_phase_chroma_frac);
+
+
+ /* Program LUT coefficients*/
+ filter_v = wbscl_get_filter_coeffs_16p(
+ v_taps_luma, tmp_v_ratio_luma);
+ filter_v_c = wbscl_get_filter_coeffs_16p(
+ v_taps_chroma, dc_fixpt_from_int(v_ratio_luma * 2));
+ wbscl_set_scaler_filter(dwbc20, v_taps_luma,
+ WBSCL_COEF_LUMA_VERT_FILTER, filter_v);
+
+ wbscl_set_scaler_filter(dwbc20, v_taps_chroma,
+ WBSCL_COEF_CHROMA_VERT_FILTER, filter_v_c);
+ return true;
+}
diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h b/drivers/gpu/drm/amd/display/dc/inc/core_types.h
index 80709c9343c1..d31dc3fe8ce8 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/core_types.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h
@@ -36,6 +36,10 @@
#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
#include "mpc.h"
#endif
+#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+#include "dwb.h"
+#include "mcif_wb.h"
+#endif
#define MAX_CLOCK_SOURCES 7
@@ -126,7 +130,18 @@ struct resource_funcs {
struct resource_context *res_ctx,
const struct resource_pool *pool,
struct dc_stream_state *stream);
+#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ void (*populate_dml_writeback_from_context)(
+ struct dc *dc,
+ struct resource_context *res_ctx,
+ display_e2e_pipe_params_st *pipes);
+ void (*set_mcif_arb_params)(
+ struct dc *dc,
+ struct dc_state *context,
+ display_e2e_pipe_params_st *pipes,
+ int pipe_cnt);
+#endif
};
struct audio_support{
@@ -154,6 +169,17 @@ struct resource_pool {
struct dce_i2c_sw *sw_i2cs[MAX_PIPES];
bool i2c_hw_buffer_in_use;
+#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ struct dwbc *dwbc[MAX_DWB_PIPES];
+ struct mcif_wb *mcif_wb[MAX_DWB_PIPES];
+ struct {
+ unsigned int gsl_0:1;
+ unsigned int gsl_1:1;
+ unsigned int gsl_2:1;
+ } gsl_groups;
+#endif
+
+
unsigned int pipe_count;
unsigned int underlay_pipe_index;
unsigned int stream_enc_count;
@@ -164,7 +190,11 @@ struct resource_pool {
unsigned int dchub_ref_clock_inKhz;
} ref_clocks;
unsigned int timing_generator_count;
+ unsigned int mpcc_count;
+#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ unsigned int writeback_pipe_count;
+#endif
/*
* reserved clock source for DP
*/
@@ -201,6 +231,12 @@ struct stream_resource {
struct encoder_info_frame encoder_info_frame;
struct abm *abm;
+#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ /* There are only (num_pipes+1)/2 groups. 0 means unassigned,
+ * otherwise it's using group number 'gsl_group-1'
+ */
+ uint8_t gsl_group;
+#endif
};
struct plane_resource {
@@ -257,6 +293,10 @@ struct pipe_ctx {
struct _vcs_dpi_display_pipe_dest_params_st pipe_dlg_param;
#endif
union pipe_update_flags update_flags;
+#ifdef CONFIG_DRM_AMD_DC_DCN2_0
+ struct dwbc *dwbc;
+ struct mcif_wb *mcif_wb;
+#endif
};
struct resource_context {
@@ -265,6 +305,9 @@ struct resource_context {
bool is_audio_acquired[MAX_PIPES];
uint8_t clock_source_ref_count[MAX_CLOCK_SOURCES];
uint8_t dp_clock_source_ref_count;
+#ifdef CONFIG_DRM_AMD_DC_DCN2_0
+ bool is_dsc_acquired[MAX_PIPES];
+#endif
};
struct dce_bw_output {
@@ -284,9 +327,18 @@ struct dce_bw_output {
int blackout_recovery_time_us;
};
+#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+struct dcn_bw_writeback {
+ struct mcif_arb_params mcif_wb_arb[MAX_DWB_PIPES];
+};
+#endif
+
struct dcn_bw_output {
struct dc_clocks clk;
struct dcn_watermark_set watermarks;
+#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ struct dcn_bw_writeback bw_writeback;
+#endif
};
union bw_output {
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dwb.h b/drivers/gpu/drm/amd/display/dc/inc/hw/dwb.h
new file mode 100644
index 000000000000..01f892dc8c91
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dwb.h
@@ -0,0 +1,187 @@
+/* Copyright 2012-17 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifndef __DC_DWBC_H__
+#define __DC_DWBC_H__
+
+#include "dc_hw_types.h"
+
+
+#define DWB_SW_V2 1
+#define DWB_MCIF_BUF_COUNT 4
+
+/* forward declaration of mcif_wb struct */
+struct mcif_wb;
+
+enum dce_version;
+
+enum dwb_sw_version {
+ dwb_ver_1_0 = 1,
+};
+
+enum dwb_source {
+ dwb_src_scl = 0, /* for DCE7x/9x, DCN won't support. */
+ dwb_src_blnd, /* for DCE7x/9x */
+ dwb_src_fmt, /* for DCE7x/9x */
+#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ dwb_src_otg0 = 0x100, /* for DCN1.x/DCN2.x, register: mmDWB_SOURCE_SELECT */
+ dwb_src_otg1, /* for DCN1.x/DCN2.x */
+ dwb_src_otg2, /* for DCN1.x/DCN2.x */
+ dwb_src_otg3, /* for DCN1.x/DCN2.x */
+#else
+ dwb_src_otg0 = 0x100, /* for DCN1.x, register: mmDWB_SOURCE_SELECT */
+ dwb_src_otg1, /* for DCN1.x */
+ dwb_src_otg2, /* for DCN1.x */
+ dwb_src_otg3, /* for DCN1.x */
+#endif
+ dwb_src_mpc0 = 0x200, /* for DCN2, register: mmMPC_DWB0_MUX, mmMPC_DWB1_MUX, mmMPC_DWB2_MUX */
+ dwb_src_mpc1, /* for DCN2 */
+ dwb_src_mpc2, /* for DCN2 */
+ dwb_src_mpc3, /* for DCN2 */
+ dwb_src_mpc4, /* for DCN2 */
+};
+
+#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+/* DCN1.x, DCN2.x support 2 pipes */
+#else
+/* DCN1.x supports 2 pipes */
+#endif
+enum dwb_pipe {
+ dwb_pipe0 = 0,
+#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
+ dwb_pipe1,
+#endif
+ dwb_pipe_max_num,
+};
+
+#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+enum dwb_frame_capture_enable {
+ DWB_FRAME_CAPTURE_DISABLE = 0,
+ DWB_FRAME_CAPTURE_ENABLE = 1,
+};
+
+enum dwb_stereo_eye_select {
+ DWB_STEREO_EYE_LEFT = 1, /* Capture left eye only */
+ DWB_STEREO_EYE_RIGHT = 2, /* Capture right eye only */
+};
+
+enum dwb_stereo_type {
+ DWB_STEREO_TYPE_FRAME_PACKING = 0, /* Frame packing */
+ DWB_STEREO_TYPE_FRAME_SEQUENTIAL = 3, /* Frame sequential */
+};
+
+enum wbscl_coef_filter_type_sel {
+ WBSCL_COEF_LUMA_VERT_FILTER = 0,
+ WBSCL_COEF_CHROMA_VERT_FILTER = 1,
+ WBSCL_COEF_LUMA_HORZ_FILTER = 2,
+ WBSCL_COEF_CHROMA_HORZ_FILTER = 3
+};
+
+#endif
+
+#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+struct dwb_stereo_params {
+ bool stereo_enabled; /* false: normal mode, true: 3D stereo */
+ enum dwb_stereo_type stereo_type; /* indicates stereo format */
+ bool stereo_polarity; /* indicates left eye or right eye comes first in stereo mode */
+ enum dwb_stereo_eye_select stereo_eye_select; /* indicate which eye should be captured */
+};
+
+struct dwb_warmup_params {
+ bool warmup_en; /* false: normal mode, true: enable pattern generator */
+ bool warmup_mode; /* false: 420, true: 444 */
+ bool warmup_depth; /* false: 8bit, true: 10bit */
+ int warmup_data; /* Data to be sent by pattern generator (same for each pixel component) */
+ int warmup_width; /* Pattern width (pixels) */
+ int warmup_height; /* Pattern height (lines) */
+};
+#endif
+
+struct dwb_caps {
+ enum dce_version hw_version; /* DCN engine version. */
+ enum dwb_sw_version sw_version; /* DWB sw implementation version. */
+ unsigned int reserved[6]; /* Reserved for future use, MUST BE 0. */
+ unsigned int adapter_id;
+ unsigned int num_pipes; /* number of DWB pipes */
+ struct {
+ unsigned int support_dwb :1;
+ unsigned int support_ogam :1;
+ unsigned int support_wbscl :1;
+ unsigned int support_ocsc :1;
+ } caps;
+ unsigned int reserved2[10]; /* Reserved for future use, MUST BE 0. */
+};
+
+struct dwbc {
+ const struct dwbc_funcs *funcs;
+ struct dc_context *ctx;
+ int inst;
+ struct mcif_wb *mcif;
+ bool status;
+ int inputSrcSelect;
+ bool dwb_output_black;
+ enum dc_transfer_func_predefined tf;
+ enum dc_color_space output_color_space;
+};
+
+struct dwbc_funcs {
+ bool (*get_caps)(
+ struct dwbc *dwbc,
+ struct dwb_caps *caps);
+
+ bool (*enable)(
+ struct dwbc *dwbc,
+ struct dc_dwb_params *params);
+
+ bool (*disable)(struct dwbc *dwbc);
+
+ bool (*update)(
+ struct dwbc *dwbc,
+ struct dc_dwb_params *params);
+
+ bool (*is_enabled)(
+ struct dwbc *dwbc);
+
+ void (*set_stereo)(
+ struct dwbc *dwbc,
+ struct dwb_stereo_params *stereo_params);
+
+ void (*set_new_content)(
+ struct dwbc *dwbc,
+ bool is_new_content);
+
+#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+
+ void (*set_warmup)(
+ struct dwbc *dwbc,
+ struct dwb_warmup_params *warmup_params);
+
+#endif
+
+ void (*dwb_set_scaler)(
+ struct dwbc *dwbc,
+ struct dc_dwb_params *params);
+};
+
+#endif
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/mcif_wb.h b/drivers/gpu/drm/amd/display/dc/inc/hw/mcif_wb.h
new file mode 100644
index 000000000000..a5c8d92fc5c2
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/mcif_wb.h
@@ -0,0 +1,105 @@
+/* Copyright 2012-17 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifndef __DC_MCIF_WB_H__
+#define __DC_MCIF_WB_H__
+
+#include "dc_hw_types.h"
+
+
+enum mmhubbub_wbif_mode {
+ PACKED_444 = 0,
+ PACKED_444_FP16 = 1,
+ PLANAR_420_8BPC = 2,
+ PLANAR_420_10BPC = 3
+};
+
+struct mcif_arb_params {
+
+ unsigned int time_per_pixel;
+ unsigned int cli_watermark[4];
+ unsigned int pstate_watermark[4];
+ unsigned int arbitration_slice;
+ unsigned int slice_lines;
+ unsigned int max_scaled_time;
+};
+
+struct mcif_irq_params {
+ unsigned int sw_int_en;
+ unsigned int sw_slice_int_en;
+ unsigned int sw_overrun_int_en;
+ unsigned int vce_int_en;
+ unsigned int vce_slice_int_en;
+};
+
+
+/* / - mcif_wb_frame_dump_info is the info of the dumping WB data */
+struct mcif_wb_frame_dump_info {
+ unsigned int size;
+ unsigned int width;
+ unsigned int height;
+ unsigned int luma_pitch;
+ unsigned int chroma_pitch;
+ enum dwb_scaler_mode format;
+};
+
+struct mcif_wb {
+ const struct mcif_wb_funcs *funcs;
+ struct dc_context *ctx;
+ int inst;
+};
+
+struct mcif_wb_funcs {
+
+ void (*enable_mcif)(struct mcif_wb *mcif_wb);
+
+ void (*disable_mcif)(struct mcif_wb *mcif_wb);
+
+ void (*config_mcif_buf)(
+ struct mcif_wb *mcif_wb,
+ struct mcif_buf_params *params,
+ unsigned int dest_height);
+
+ void (*config_mcif_arb)(
+ struct mcif_wb *mcif_wb,
+ struct mcif_arb_params *params);
+
+ void (*config_mcif_irq)(
+ struct mcif_wb *mcif_wb,
+ struct mcif_irq_params *params);
+
+ void (*dump_frame)(
+ struct mcif_wb *mcif_wb,
+ struct mcif_buf_params *mcif_params,
+ enum dwb_scaler_mode out_format,
+ unsigned int dest_width,
+ unsigned int dest_height,
+ struct mcif_wb_frame_dump_info *dump_info,
+ unsigned char *luma_buffer,
+ unsigned char *chroma_buffer,
+ unsigned char *dest_luma_buffer,
+ unsigned char *dest_chroma_buffer);
+};
+
+#endif
--
2.20.1
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