[PATCH 247/459] Revert "drm/amdgpu: mask some pm interfaces for navi10 because they are changed or not workable so far"

Christian K├Ânig ckoenig.leichtzumerken at gmail.com
Tue Jun 18 07:58:28 UTC 2019


Am 17.06.19 um 21:30 schrieb Alex Deucher:
> From: Kevin Wang <kevin1.wang at amd.com>
>
> This reverts commit fd9c75d217d5b4ed72672722b6621e2635363dfe.
>
> Signed-off-by: Kevin Wang <kevin1.wang at amd.com>
> Reviewed-by: Huang Rui <ray.huang at amd.com>
> Signed-off-by: Alex Deucher <alexander.deucher at amd.com>

Would it be possible to squash that into the original commit which 
disabled things?

Christian.

> ---
>   drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c |   2 +-
>   drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c  | 156 +++++++++++-------------
>   2 files changed, 73 insertions(+), 85 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
> index af86d9f47785..ed051fdb509f 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
> @@ -690,7 +690,7 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file
>   		dev_info.num_shader_arrays_per_engine = adev->gfx.config.max_sh_per_se;
>   		/* return all clocks in KHz */
>   		dev_info.gpu_counter_freq = amdgpu_asic_get_xclk(adev) * 10;
> -		if (adev->pm.dpm_enabled && adev->asic_type != CHIP_NAVI10) {
> +		if (adev->pm.dpm_enabled) {
>   			dev_info.max_engine_clock = amdgpu_dpm_get_sclk(adev, false) * 10;
>   			dev_info.max_memory_clock = amdgpu_dpm_get_mclk(adev, false) * 10;
>   		} else if (amdgpu_sriov_vf(adev) && amdgim_is_hwperf(adev) &&
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
> index 8c28f816b50f..6b97f3098118 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
> @@ -2793,33 +2793,32 @@ int amdgpu_pm_sysfs_init(struct amdgpu_device *adev)
>   		return ret;
>   	}
>   
> -	if (adev->asic_type != CHIP_NAVI10) {
> -		ret = device_create_file(adev->dev, &dev_attr_power_dpm_state);
> -		if (ret) {
> -			DRM_ERROR("failed to create device file for dpm state\n");
> -			return ret;
> -		}
> -		ret = device_create_file(adev->dev, &dev_attr_power_dpm_force_performance_level);
> -		if (ret) {
> -			DRM_ERROR("failed to create device file for dpm state\n");
> -			return ret;
> -		}
> +	ret = device_create_file(adev->dev, &dev_attr_power_dpm_state);
> +	if (ret) {
> +		DRM_ERROR("failed to create device file for dpm state\n");
> +		return ret;
> +	}
> +	ret = device_create_file(adev->dev, &dev_attr_power_dpm_force_performance_level);
> +	if (ret) {
> +		DRM_ERROR("failed to create device file for dpm state\n");
> +		return ret;
> +	}
>   
> -		ret = device_create_file(adev->dev, &dev_attr_pp_num_states);
> -		if (ret) {
> -			DRM_ERROR("failed to create device file pp_num_states\n");
> -			return ret;
> -		}
> -		ret = device_create_file(adev->dev, &dev_attr_pp_cur_state);
> -		if (ret) {
> -			DRM_ERROR("failed to create device file pp_cur_state\n");
> -			return ret;
> -		}
> -		ret = device_create_file(adev->dev, &dev_attr_pp_force_state);
> -		if (ret) {
> -			DRM_ERROR("failed to create device file pp_force_state\n");
> -			return ret;
> -		}
> +
> +	ret = device_create_file(adev->dev, &dev_attr_pp_num_states);
> +	if (ret) {
> +		DRM_ERROR("failed to create device file pp_num_states\n");
> +		return ret;
> +	}
> +	ret = device_create_file(adev->dev, &dev_attr_pp_cur_state);
> +	if (ret) {
> +		DRM_ERROR("failed to create device file pp_cur_state\n");
> +		return ret;
> +	}
> +	ret = device_create_file(adev->dev, &dev_attr_pp_force_state);
> +	if (ret) {
> +		DRM_ERROR("failed to create device file pp_force_state\n");
> +		return ret;
>   	}
>   	ret = device_create_file(adev->dev, &dev_attr_pp_table);
>   	if (ret) {
> @@ -2832,55 +2831,52 @@ int amdgpu_pm_sysfs_init(struct amdgpu_device *adev)
>   		DRM_ERROR("failed to create device file pp_dpm_sclk\n");
>   		return ret;
>   	}
> -
> -	if (adev->asic_type != CHIP_NAVI10) {
> -		ret = device_create_file(adev->dev, &dev_attr_pp_dpm_mclk);
> -		if (ret) {
> -			DRM_ERROR("failed to create device file pp_dpm_mclk\n");
> -			return ret;
> -		}
> -		if (adev->asic_type >= CHIP_VEGA10) {
> -			ret = device_create_file(adev->dev, &dev_attr_pp_dpm_socclk);
> -			if (ret) {
> -				DRM_ERROR("failed to create device file pp_dpm_socclk\n");
> -				return ret;
> -			}
> -			ret = device_create_file(adev->dev, &dev_attr_pp_dpm_dcefclk);
> -			if (ret) {
> -				DRM_ERROR("failed to create device file pp_dpm_dcefclk\n");
> -				return ret;
> -			}
> -		}
> -		if (adev->asic_type >= CHIP_VEGA20) {
> -			ret = device_create_file(adev->dev, &dev_attr_pp_dpm_fclk);
> -			if (ret) {
> -				DRM_ERROR("failed to create device file pp_dpm_fclk\n");
> -				return ret;
> -			}
> -		}
> -		ret = device_create_file(adev->dev, &dev_attr_pp_dpm_pcie);
> -		if (ret) {
> -			DRM_ERROR("failed to create device file pp_dpm_pcie\n");
> -			return ret;
> -		}
> -		ret = device_create_file(adev->dev, &dev_attr_pp_sclk_od);
> +	ret = device_create_file(adev->dev, &dev_attr_pp_dpm_mclk);
> +	if (ret) {
> +		DRM_ERROR("failed to create device file pp_dpm_mclk\n");
> +		return ret;
> +	}
> +	if (adev->asic_type >= CHIP_VEGA10) {
> +		ret = device_create_file(adev->dev, &dev_attr_pp_dpm_socclk);
>   		if (ret) {
> -			DRM_ERROR("failed to create device file pp_sclk_od\n");
> +			DRM_ERROR("failed to create device file pp_dpm_socclk\n");
>   			return ret;
>   		}
> -		ret = device_create_file(adev->dev, &dev_attr_pp_mclk_od);
> +		ret = device_create_file(adev->dev, &dev_attr_pp_dpm_dcefclk);
>   		if (ret) {
> -			DRM_ERROR("failed to create device file pp_mclk_od\n");
> +			DRM_ERROR("failed to create device file pp_dpm_dcefclk\n");
>   			return ret;
>   		}
> -		ret = device_create_file(adev->dev,
> -				&dev_attr_pp_power_profile_mode);
> +	}
> +	if (adev->asic_type >= CHIP_VEGA20) {
> +		ret = device_create_file(adev->dev, &dev_attr_pp_dpm_fclk);
>   		if (ret) {
> -			DRM_ERROR("failed to create device file	"
> -					"pp_power_profile_mode\n");
> +			DRM_ERROR("failed to create device file pp_dpm_fclk\n");
>   			return ret;
>   		}
>   	}
> +	ret = device_create_file(adev->dev, &dev_attr_pp_dpm_pcie);
> +	if (ret) {
> +		DRM_ERROR("failed to create device file pp_dpm_pcie\n");
> +		return ret;
> +	}
> +	ret = device_create_file(adev->dev, &dev_attr_pp_sclk_od);
> +	if (ret) {
> +		DRM_ERROR("failed to create device file pp_sclk_od\n");
> +		return ret;
> +	}
> +	ret = device_create_file(adev->dev, &dev_attr_pp_mclk_od);
> +	if (ret) {
> +		DRM_ERROR("failed to create device file pp_mclk_od\n");
> +		return ret;
> +	}
> +	ret = device_create_file(adev->dev,
> +			&dev_attr_pp_power_profile_mode);
> +	if (ret) {
> +		DRM_ERROR("failed to create device file	"
> +				"pp_power_profile_mode\n");
> +		return ret;
> +	}
>   	if ((is_support_sw_smu(adev) && adev->smu.od_enabled) ||
>   	    (!is_support_sw_smu(adev) && hwmgr->od_enabled)) {
>   		ret = device_create_file(adev->dev,
> @@ -3056,25 +3052,21 @@ static int amdgpu_debugfs_pm_info_pp(struct seq_file *m, struct amdgpu_device *a
>   	/* GPU Clocks */
>   	size = sizeof(value);
>   	seq_printf(m, "GFX Clocks and Power:\n");
> -	if (adev->asic_type != CHIP_NAVI10) {
> -		if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_MCLK, (void *)&value, &size))
> -			seq_printf(m, "\t%u MHz (MCLK)\n", value/100);
> -		if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_SCLK, (void *)&value, &size))
> -			seq_printf(m, "\t%u MHz (SCLK)\n", value/100);
> -		if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK, (void *)&value, &size))
> -			seq_printf(m, "\t%u MHz (PSTATE_SCLK)\n", value/100);
> -		if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK, (void *)&value, &size))
> -			seq_printf(m, "\t%u MHz (PSTATE_MCLK)\n", value/100);
> -	}
> +	if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_MCLK, (void *)&value, &size))
> +		seq_printf(m, "\t%u MHz (MCLK)\n", value/100);
> +	if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_SCLK, (void *)&value, &size))
> +		seq_printf(m, "\t%u MHz (SCLK)\n", value/100);
> +	if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK, (void *)&value, &size))
> +		seq_printf(m, "\t%u MHz (PSTATE_SCLK)\n", value/100);
> +	if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK, (void *)&value, &size))
> +		seq_printf(m, "\t%u MHz (PSTATE_MCLK)\n", value/100);
>   	if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDGFX, (void *)&value, &size))
>   		seq_printf(m, "\t%u mV (VDDGFX)\n", value);
>   	if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDNB, (void *)&value, &size))
>   		seq_printf(m, "\t%u mV (VDDNB)\n", value);
> -	if (adev->asic_type != CHIP_NAVI10) {
> -		size = sizeof(uint32_t);
> -		if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_POWER, (void *)&query, &size))
> -			seq_printf(m, "\t%u.%u W (average GPU)\n", query >> 8, query & 0xff);
> -	}
> +	size = sizeof(uint32_t);
> +	if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_POWER, (void *)&query, &size))
> +		seq_printf(m, "\t%u.%u W (average GPU)\n", query >> 8, query & 0xff);
>   	size = sizeof(value);
>   	seq_printf(m, "\n");
>   
> @@ -3082,10 +3074,6 @@ static int amdgpu_debugfs_pm_info_pp(struct seq_file *m, struct amdgpu_device *a
>   	if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_TEMP, (void *)&value, &size))
>   		seq_printf(m, "GPU Temperature: %u C\n", value/1000);
>   
> -	/* TODO: will be removed after gpu load, feature mask, uvd/vce clocks enabled on navi10 */
> -	if (adev->asic_type == CHIP_NAVI10)
> -		return 0;
> -
>   	/* GPU Load */
>   	if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_LOAD, (void *)&value, &size))
>   		seq_printf(m, "GPU Load: %u %%\n", value);



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