[PATCH] drm/amd/amdgpu: Add ENGINE_CNTL register to vcn10 headers

[Tom St Denis]

Hi,

Alex can I get an RB on this :-)

Thanks,
Tom

On Mon, Mar 4, 2019 at 10:59 AM StDenis, Tom <Tom.StDenis at amd.com> wrote:

> Signed-off-by: Tom St Denis <tom.stdenis at amd.com>
> ---
>  drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_offset.h  | 2 ++
>  drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h | 5 +++++
>  2 files changed, 7 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_offset.h
> b/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_offset.h
> index 442ca7c471a5..6109f5ad25ad 100644
> --- a/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_offset.h
> +++ b/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_offset.h
> @@ -141,6 +141,8 @@
>  #define mmUVD_GPCOM_VCPU_DATA0_BASE_IDX
>                               1
>  #define mmUVD_GPCOM_VCPU_DATA1
>                              0x03c5
>  #define mmUVD_GPCOM_VCPU_DATA1_BASE_IDX
>                               1
> +#define mmUVD_ENGINE_CNTL
>                               0x03c6
> +#define mmUVD_ENGINE_CNTL_BASE_IDX
>                              1
>  #define mmUVD_UDEC_DBW_UV_ADDR_CONFIG
>                               0x03d2
>  #define mmUVD_UDEC_DBW_UV_ADDR_CONFIG_BASE_IDX
>                              1
>  #define mmUVD_UDEC_ADDR_CONFIG
>                              0x03d3
> diff --git a/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h
> b/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h
> index 63457f9df4c5..f84bed6eecb9 100644
> --- a/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h
> +++ b/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h
> @@ -312,6 +312,11 @@
>  //UVD_GPCOM_VCPU_DATA1
>  #define UVD_GPCOM_VCPU_DATA1__DATA1__SHIFT
>                                     0x0
>  #define UVD_GPCOM_VCPU_DATA1__DATA1_MASK
>                                     0xFFFFFFFFL
> +//UVD_ENGINE_CNTL
> +#define UVD_ENGINE_CNTL__ENGINE_START_MASK 0x1
> +#define UVD_ENGINE_CNTL__ENGINE_START__SHIFT 0x0
> +#define UVD_ENGINE_CNTL__ENGINE_START_MODE_MASK 0x2
> +#define UVD_ENGINE_CNTL__ENGINE_START_MODE__SHIFT 0x1
>  //UVD_UDEC_DBW_UV_ADDR_CONFIG
>  #define UVD_UDEC_DBW_UV_ADDR_CONFIG__NUM_PIPES__SHIFT
>                                      0x0
>  #define UVD_UDEC_DBW_UV_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT
>                                     0x3
> --
> 2.17.2
>
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