[PATCH] drm/amdgpu: reroute VMC and UMD to IH ring 1

[Christian König]

Oh, indeed. Nobody noticed so far and the patch is already committed.

Christian.

Am 05.03.19 um 16:25 schrieb Zeng, Oak:
> Is the "UMD" in the title a typo? From the comments in the code it is "UMC"
>
> Regards,
> Oak
>
> -----Original Message-----
> From: amd-gfx <amd-gfx-bounces at lists.freedesktop.org> On Behalf Of Christian König
> Sent: Monday, March 4, 2019 8:15 AM
> To: amd-gfx at lists.freedesktop.org
> Subject: [PATCH] drm/amdgpu: reroute VMC and UMD to IH ring 1
>
> Page faults can easily overwhelm the interrupt handler.
>
> So to make sure that we never lose valuable interrupts on the primary ring we re-route page faults to IH ring 1.
>
> Signed-off-by: Christian König <christian.koenig at amd.com>
> ---
>   drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h |  1 +
>   drivers/gpu/drm/amd/amdgpu/psp_v3_1.c   | 36 +++++++++++++++++++++++++
>   2 files changed, 37 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h b/drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h
> index f3a7d207af07..2f79765b4bdb 100644
> --- a/drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h
> +++ b/drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h
> @@ -43,6 +43,7 @@ enum psp_gfx_crtl_cmd_id
>       GFX_CTRL_CMD_ID_ENABLE_INT      = 0x00050000,   /* enable PSP-to-Gfx interrupt */
>       GFX_CTRL_CMD_ID_DISABLE_INT     = 0x00060000,   /* disable PSP-to-Gfx interrupt */
>       GFX_CTRL_CMD_ID_MODE1_RST       = 0x00070000,   /* trigger the Mode 1 reset */
> +    GFX_CTRL_CMD_ID_GBR_IH_SET      = 0x00080000,   /* set Gbr IH_RB_CNTL registers */
>       GFX_CTRL_CMD_ID_CONSUME_CMD     = 0x000A0000,   /* send interrupt to psp for updating write pointer of vf */
>       GFX_CTRL_CMD_ID_DESTROY_GPCOM_RING = 0x000C0000, /* destroy GPCOM ring */
>   
> diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c b/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
> index 0487e3a4e9e7..143f0fae69d5 100644
> --- a/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
> +++ b/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
> @@ -37,6 +37,9 @@
>   #include "sdma0/sdma0_4_0_offset.h"
>   #include "nbio/nbio_6_1_offset.h"
>   
> +#include "oss/osssys_4_0_offset.h"
> +#include "oss/osssys_4_0_sh_mask.h"
> +
>   MODULE_FIRMWARE("amdgpu/vega10_sos.bin");
>   MODULE_FIRMWARE("amdgpu/vega10_asd.bin");
>   MODULE_FIRMWARE("amdgpu/vega12_sos.bin");
> @@ -252,6 +255,37 @@ static int psp_v3_1_ring_init(struct psp_context *psp,
>   	return 0;
>   }
>   
> +static void psp_v3_1_reroute_ih(struct psp_context *psp) {
> +	struct amdgpu_device *adev = psp->adev;
> +	uint32_t tmp;
> +
> +	/* Change IH ring for VMC */
> +	tmp = REG_SET_FIELD(0, IH_CLIENT_CFG_DATA, CREDIT_RETURN_ADDR, 0x1244b);
> +	tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, CLIENT_TYPE, 1);
> +	tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1);
> +
> +	WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, 3);
> +	WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, tmp);
> +	WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, GFX_CTRL_CMD_ID_GBR_IH_SET);
> +
> +	mdelay(20);
> +	psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
> +		     0x80000000, 0x8000FFFF, false);
> +
> +	/* Change IH ring for UMC */
> +	tmp = REG_SET_FIELD(0, IH_CLIENT_CFG_DATA, CREDIT_RETURN_ADDR, 0x1216b);
> +	tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1);
> +
> +	WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, 4);
> +	WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, tmp);
> +	WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, GFX_CTRL_CMD_ID_GBR_IH_SET);
> +
> +	mdelay(20);
> +	psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
> +		     0x80000000, 0x8000FFFF, false);
> +}
> +
>   static int psp_v3_1_ring_create(struct psp_context *psp,
>   				enum psp_ring_type ring_type)
>   {
> @@ -260,6 +294,8 @@ static int psp_v3_1_ring_create(struct psp_context *psp,
>   	struct psp_ring *ring = &psp->km_ring;
>   	struct amdgpu_device *adev = psp->adev;
>   
> +	psp_v3_1_reroute_ih(psp);
> +
>   	/* Write low address of the ring to C2PMSG_69 */
>   	psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
>   	WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, psp_ring_reg);
> --
> 2.17.1
>
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