[PATCH 1/3] drm/amdgpu: change Vega IH ring 1 config
Christian König
ckoenig.leichtzumerken at gmail.com
Wed Mar 6 09:28:50 UTC 2019
Ping? Can anybody review this?
Thanks,
Christian.
Am 04.03.19 um 20:10 schrieb Christian König:
> Disable overflow and enable full drain. This makes fault handling on ring 1
> much more reliable since we don't generate back pressure any more.
>
> Signed-off-by: Christian König <christian.koenig at amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/vega10_ih.c | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
> index 6d1f804277f8..d4a3cc413af8 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
> @@ -203,6 +203,10 @@ static int vega10_ih_irq_init(struct amdgpu_device *adev)
>
> ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1);
> ih_rb_cntl = vega10_ih_rb_cntl(ih, ih_rb_cntl);
> + ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,
> + WPTR_OVERFLOW_ENABLE, 0);
> + ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,
> + RB_FULL_DRAIN_ENABLE, 1);
> WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl);
>
> /* set rptr, wptr to 0 */
More information about the amd-gfx
mailing list