[PATCH] drm/amdgpu: force to use CPU_ACCESS hint optimization

[Christian König]

Am 06.03.19 um 13:00 schrieb Zhou, David(ChunMing):
>
>> -----Original Message-----
>> From: Christian König <ckoenig.leichtzumerken at gmail.com>
>> Sent: Wednesday, March 06, 2019 7:55 PM
>> To: Zhou, David(ChunMing) <David1.Zhou at amd.com>; Koenig, Christian
>> <Christian.Koenig at amd.com>; amd-gfx at lists.freedesktop.org
>> Subject: Re: [PATCH] drm/amdgpu: force to use CPU_ACCESS hint
>> optimization
>>
>> Am 06.03.19 um 12:52 schrieb Chunming Zhou:
>>> As we know, visible vram can be placed to invisible when no cpu access.
>>>
>>> Signed-off-by: Chunming Zhou <david1.zhou at amd.com>
>>> ---
>>>    drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 8 +++-----
>>>    1 file changed, 3 insertions(+), 5 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
>>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
>>> index bc62bf41b7e9..823deb66f5da 100644
>>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
>>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
>>> @@ -592,8 +592,7 @@ static int amdgpu_info_ioctl(struct drm_device
>>> *dev, void *data, struct drm_file
>>>
>>>    		vram_gtt.vram_size = adev->gmc.real_vram_size -
>>>    			atomic64_read(&adev->vram_pin_size);
>>> -		vram_gtt.vram_cpu_accessible_size = adev-
>>> gmc.visible_vram_size -
>>> -			atomic64_read(&adev->visible_pin_size);
>>> +		vram_gtt.vram_cpu_accessible_size = vram_gtt.vram_size;
>> Well, NAK that would of course report the full VRAM as visible which isn't
>> correct.
> UMD also said same reason that they like report explicit vram info to application.

Yeah, I mean that is a rather good argument. The application should 
certainly know that.

> No idea to do that.

Well if I understood that correctly Vulkan had the same problem with 
cached and uncached system memory. How is it handled there?

Christian.

>
> -David
>> Christian.
>>
>>>    		vram_gtt.gtt_size = adev-
>>> mman.bdev.man[TTM_PL_TT].size;
>>>    		vram_gtt.gtt_size *= PAGE_SIZE;
>>>    		vram_gtt.gtt_size -= atomic64_read(&adev->gart_pin_size);
>>> @@ -612,9 +611,8 @@ static int amdgpu_info_ioctl(struct drm_device
>> *dev, void *data, struct drm_file
>>>    		mem.vram.max_allocation = mem.vram.usable_heap_size *
>> 3 / 4;
>>>    		mem.cpu_accessible_vram.total_heap_size =
>>> -			adev->gmc.visible_vram_size;
>>> -		mem.cpu_accessible_vram.usable_heap_size = adev-
>>> gmc.visible_vram_size -
>>> -			atomic64_read(&adev->visible_pin_size);
>>> +			mem.vram.total_heap_size;
>>> +		mem.cpu_accessible_vram.usable_heap_size =
>>> +mem.vram.usable_heap_size;
>>>    		mem.cpu_accessible_vram.heap_usage =
>>>    			amdgpu_vram_mgr_vis_usage(&adev-
>>> mman.bdev.man[TTM_PL_VRAM]);
>>>    		mem.cpu_accessible_vram.max_allocation =
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