[PATCH libdrm 3/4] tests/amdgpu: add memset draw test
Cui, Flora
Flora.Cui at amd.com
Fri Mar 15 08:51:18 UTC 2019
add memset draw test for gfx9
Change-Id: I3a1f2460ec0917e29ce1a891200eeaa1a0565fda
Signed-off-by: Flora Cui <flora.cui at amd.com>
Tested-by: Rui Teng <rui.teng at amd.com>
---
tests/amdgpu/amdgpu_test.c | 5 +
tests/amdgpu/basic_tests.c | 554 +++++++++++++++++++++++++++++++++++++++++++++
2 files changed, 559 insertions(+)
diff --git a/tests/amdgpu/amdgpu_test.c b/tests/amdgpu/amdgpu_test.c
index 35324cb..0b870de 100644
--- a/tests/amdgpu/amdgpu_test.c
+++ b/tests/amdgpu/amdgpu_test.c
@@ -441,6 +441,11 @@ static void amdgpu_disable_suites()
if (family_id < AMDGPU_FAMILY_AI || family_id > AMDGPU_FAMILY_RV)
if (amdgpu_set_test_active(BASIC_TESTS_STR, "Dispatch Test", CU_FALSE))
fprintf(stderr, "test deactivation failed - %s\n", CU_get_error_msg());
+
+ /* This test was ran on GFX9 only */
+ if (family_id < AMDGPU_FAMILY_AI || family_id > AMDGPU_FAMILY_RV)
+ if (amdgpu_set_test_active(BASIC_TESTS_STR, "Draw Test", CU_FALSE))
+ fprintf(stderr, "test deactivation failed - %s\n", CU_get_error_msg());
}
/* The main() function for setting up and running the tests.
diff --git a/tests/amdgpu/basic_tests.c b/tests/amdgpu/basic_tests.c
index 2f559f4..0ba6199 100644
--- a/tests/amdgpu/basic_tests.c
+++ b/tests/amdgpu/basic_tests.c
@@ -50,6 +50,7 @@ static void amdgpu_semaphore_test(void);
static void amdgpu_sync_dependency_test(void);
static void amdgpu_bo_eviction_test(void);
static void amdgpu_dispatch_test(void);
+static void amdgpu_draw_test(void);
static void amdgpu_command_submission_write_linear_helper(unsigned ip_type);
static void amdgpu_command_submission_const_fill_helper(unsigned ip_type);
@@ -72,6 +73,7 @@ CU_TestInfo basic_tests[] = {
{ "SW semaphore Test", amdgpu_semaphore_test },
{ "Sync dependency Test", amdgpu_sync_dependency_test },
{ "Dispatch Test", amdgpu_dispatch_test },
+ { "Draw Test", amdgpu_draw_test },
CU_TEST_INFO_NULL,
};
#define BUFFER_SIZE (8 * 1024)
@@ -318,6 +320,99 @@ static const uint32_t buffercopy_cs_shader_gfx9[] = {
0xBF8C0F70, 0xE01C2000, 0x80010100, 0xBF810000
};
+static const uint32_t preamblecache_gfx9[] = {
+ 0xc0026900, 0x81, 0x80000000, 0x40004000, 0xc0026900, 0x8c, 0xaa99aaaa, 0x0,
+ 0xc0026900, 0x90, 0x80000000, 0x40004000, 0xc0026900, 0x94, 0x80000000, 0x40004000,
+ 0xc0026900, 0xb4, 0x0, 0x3f800000, 0xc0016900, 0x103, 0x0,
+ 0xc0016900, 0x208, 0x0, 0xc0016900, 0x290, 0x0,
+ 0xc0016900, 0x2a1, 0x0, 0xc0026900, 0x2ad, 0x0, 0x0,
+ 0xc0016900, 0x2d5, 0x10000, 0xc0016900, 0x2dc, 0x0,
+ 0xc0066900, 0x2de, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xc0026900, 0x2e5, 0x0, 0x0,
+ 0xc0056900, 0x2f9, 0x5, 0x3f800000, 0x3f800000, 0x3f800000, 0x3f800000,
+ 0xc0026900, 0x311, 0x3, 0x0, 0xc0026900, 0x316, 0x1e, 0x20,
+ 0xc0016900, 0x349, 0x0, 0xc0016900, 0x358, 0x0, 0xc0016900, 0x367, 0x0,
+ 0xc0016900, 0x376, 0x0, 0xc0016900, 0x385, 0x0, 0xc0016900, 0x19, 0x0,
+ 0xc0056900, 0xe8, 0x0, 0x0, 0x0, 0x0, 0x0,
+ 0xc0076900, 0x1e1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
+ 0xc0026900, 0x204, 0x90000, 0x4, 0xc0046900, 0x20c, 0x0, 0x0, 0x0, 0x0,
+ 0xc0016900, 0x2b2, 0x0, 0xc0026900, 0x30e, 0xffffffff, 0xffffffff,
+ 0xc0016900, 0x314, 0x0, 0xc0002f00, 0x1, 0xc0016900, 0x1, 0x1,
+ 0xc0016900, 0x18, 0x2, 0xc0016900, 0x206, 0x300, 0xc0017900, 0x20000243, 0x0,
+ 0xc0017900, 0x248, 0xffffffff, 0xc0017900, 0x249, 0x0, 0xc0017900, 0x24a, 0x0,
+ 0xc0017900, 0x24b, 0x0
+};
+
+enum ps_type {
+ PS_CONST
+};
+
+static const uint32_t ps_const_shader_gfx9[] = {
+ 0x7E000200, 0x7E020201, 0x7E040202, 0x7E060203,
+ 0xD2960000, 0x00020300, 0xD2960001, 0x00020702,
+ 0xC4001C0F, 0x00000100, 0xBF810000
+};
+
+static const uint32_t ps_const_shader_patchinfo_code_size_gfx9 = 6;
+
+static const uint32_t ps_const_shader_patchinfo_code_gfx9[][10][6] = {
+ {{ 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xC4001890, 0x00000000 },
+ { 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xC4001801, 0x00000000 },
+ { 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xC4001803, 0x00000100 },
+ { 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xC4001803, 0x00000300 },
+ { 0xD2960000, 0x00020300, 0xD2960001, 0x00020702, 0xC4001C0F, 0x00000100 },
+ { 0xD2950000, 0x00020300, 0xD2950001, 0x00020702, 0xC4001C0F, 0x00000100 },
+ { 0xD2940000, 0x00020300, 0xD2940001, 0x00020702, 0xC4001C0F, 0x00000100 },
+ { 0xD2970000, 0x00020300, 0xD2970001, 0x00020702, 0xC4001C0F, 0x00000100 },
+ { 0xD2980000, 0x00020300, 0xD2980001, 0x00020702, 0xC4001C0F, 0x00000100 },
+ { 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xC400180F, 0x03020100 }
+ }
+};
+
+static const uint32_t ps_const_shader_patchinfo_offset_gfx9[] = {
+ 0x00000004
+};
+
+static const uint32_t ps_num_sh_registers_gfx9 = 2;
+
+static const uint32_t ps_const_sh_registers_gfx9[][2] = {
+ {0x2C0A, 0x000C0040},//{ mmSPI_SHADER_PGM_RSRC1_PS, 0x000C0040 },
+ {0x2C0B, 0x00000008}, //{ mmSPI_SHADER_PGM_RSRC2_PS, 0x00000008 }
+};
+
+static const uint32_t ps_num_context_registers_gfx9 = 7;
+
+static const uint32_t ps_const_context_reg_gfx9[][2] = {
+ {0xA1B4, 0x00000002}, //{ mmSPI_PS_INPUT_ADDR, 0x00000002 },
+ {0xA1B6, 0x00000000}, //{ mmSPI_PS_IN_CONTROL, 0x00000000 },
+ {0xA08F, 0x0000000F}, //{ mmCB_SHADER_MASK, 0x0000000F },
+ {0xA203, 0x00000010}, //{ mmDB_SHADER_CONTROL, 0x00000010 },
+ {0xA1C4, 0x00000000}, //{ mmSPI_SHADER_Z_FORMAT, 0x00000000 },
+ {0xA1B8, 0x00000000}, //{ mmSPI_BARYC_CNTL, 0x00000000 /* Always 0 for now */},
+ {0xA1C5, 0x00000004}, //{ mmSPI_SHADER_COL_FORMAT, 0x00000004 }
+};
+
+static const uint32_t vs_RectPosTexFast_shader_gfx9[] = {
+ 0x7E000B00, 0x020000F3, 0xD042000A, 0x00010100,
+ 0x7E020202, 0x7E040200, 0x020000F3, 0x7E060206,
+ 0x7E080204, 0xD1000001, 0x002A0302, 0x7C840080,
+ 0x7E000200, 0x7E040203, 0x7E0A0201, 0xD1000003,
+ 0x002A0704, 0x7E0C0207, 0x7E0E0205, 0x00000101,
+ 0x00020505, 0x7E040208, 0x7E0A02F2, 0x00060903,
+ 0x00080D07, 0x7E0C0209, 0xC40008CF, 0x05020100,
+ 0xC400020F, 0x05060403, 0xBF810000
+};
+
+static const uint32_t cached_cmd_gfx9[] = {
+ 0xc0016900, 0x0, 0x0, 0xc0026900, 0x3, 0x2a, 0x0,
+ 0xc0046900, 0xa, 0x0, 0x0, 0x0, 0x200020,
+ 0xc0016900, 0x83, 0xffff, 0xc0026900, 0x8e, 0xf, 0xf,
+ 0xc0056900, 0x105, 0x0, 0x0, 0x0, 0x0, 0x12,
+ 0xc0026900, 0x10b, 0x0, 0x0, 0xc0016900, 0x1e0, 0x0,
+ 0xc0036900, 0x200, 0x0, 0x10000, 0xcc0011,
+ 0xc0026900, 0x292, 0x20, 0x60201b8,
+ 0xc0026900, 0x2b0, 0x0, 0x0, 0xc0016900, 0x2f8, 0x0
+};
+
int amdgpu_bo_alloc_and_map_raw(amdgpu_device_handle dev, unsigned size,
unsigned alignment, unsigned heap, uint64_t alloc_flags,
uint64_t mapping_flags, amdgpu_bo_handle *bo, void **cpu,
@@ -2311,3 +2406,462 @@ static void amdgpu_dispatch_test(void)
amdgpu_memcpy_dispatch_test(device_handle, AMDGPU_HW_IP_GFX, ring_id);
}
}
+
+static int amdgpu_draw_load_ps_shader(uint8_t *ptr, int ps_type)
+{
+ int i;
+ uint32_t shader_offset= 256;
+ uint32_t mem_offset, patch_code_offset;
+ uint32_t shader_size, patchinfo_code_size;
+ const uint32_t *shader;
+ const uint32_t *patchinfo_code;
+ const uint32_t *patchcode_offset;
+
+ switch (ps_type) {
+ case PS_CONST:
+ shader = ps_const_shader_gfx9;
+ shader_size = sizeof(ps_const_shader_gfx9);
+ patchinfo_code = (const uint32_t *)ps_const_shader_patchinfo_code_gfx9;
+ patchinfo_code_size = ps_const_shader_patchinfo_code_size_gfx9;
+ patchcode_offset = ps_const_shader_patchinfo_offset_gfx9;
+ break;
+ default:
+ return -1;
+ break;
+ }
+
+ /* write main shader program */
+ for (i = 0 ; i < 10; i++) {
+ mem_offset = i * shader_offset;
+ memcpy(ptr + mem_offset, shader, shader_size);
+ }
+
+ /* overwrite patch codes */
+ for (i = 0 ; i < 10; i++) {
+ mem_offset = i * shader_offset + patchcode_offset[0] * sizeof(uint32_t);
+ patch_code_offset = i * patchinfo_code_size;
+ memcpy(ptr + mem_offset,
+ patchinfo_code + patch_code_offset,
+ patchinfo_code_size * sizeof(uint32_t));
+ }
+
+ return 0;
+}
+
+/* load RectPosTexFast_VS */
+static int amdgpu_draw_load_vs_shader(uint8_t *ptr)
+{
+ const uint32_t *shader;
+ uint32_t shader_size;
+
+ shader = vs_RectPosTexFast_shader_gfx9;
+ shader_size = sizeof(vs_RectPosTexFast_shader_gfx9);
+
+ memcpy(ptr, shader, shader_size);
+
+ return 0;
+}
+
+static int amdgpu_draw_init(uint32_t *ptr)
+{
+ int i = 0;
+ const uint32_t *preamblecache_ptr;
+ uint32_t preamblecache_size;
+
+ /* Write context control and load shadowing register if necessary */
+ ptr[i++] = PACKET3(PKT3_CONTEXT_CONTROL, 1);
+ ptr[i++] = 0x80000000;
+ ptr[i++] = 0x80000000;
+
+ preamblecache_ptr = preamblecache_gfx9;
+ preamblecache_size = sizeof(preamblecache_gfx9);
+
+ memcpy(ptr + i, preamblecache_ptr, preamblecache_size);
+ return i + preamblecache_size/sizeof(uint32_t);
+}
+
+static int amdgpu_draw_setup_and_write_drawblt_surf_info(uint32_t *ptr,
+ uint64_t dst_addr)
+{
+ int i = 0;
+
+ /* setup color buffer */
+ /* offset reg
+ 0xA318 CB_COLOR0_BASE
+ 0xA319 CB_COLOR0_BASE_EXT
+ 0xA31A CB_COLOR0_ATTRIB2
+ 0xA31B CB_COLOR0_VIEW
+ 0xA31C CB_COLOR0_INFO
+ 0xA31D CB_COLOR0_ATTRIB
+ 0xA31E CB_COLOR0_DCC_CONTROL
+ 0xA31F CB_COLOR0_CMASK
+ 0xA320 CB_COLOR0_CMASK_BASE_EXT
+ 0xA321 CB_COLOR0_FMASK
+ 0xA322 CB_COLOR0_FMASK_BASE_EXT
+ 0xA323 CB_COLOR0_CLEAR_WORD0
+ 0xA324 CB_COLOR0_CLEAR_WORD1
+ 0xA325 CB_COLOR0_DCC_BASE
+ 0xA326 CB_COLOR0_DCC_BASE_EXT */
+ ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 15);
+ ptr[i++] = 0x318;
+ ptr[i++] = dst_addr >> 8;
+ ptr[i++] = dst_addr >> 40;
+ ptr[i++] = 0x7c01f;
+ ptr[i++] = 0;
+ ptr[i++] = 0x50438;
+ ptr[i++] = 0x10140000;
+ i += 9;
+
+ /* mmCB_MRT0_EPITCH */
+ ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 1);
+ ptr[i++] = 0x1e8;
+ ptr[i++] = 0x1f;
+
+ /* 0xA32B CB_COLOR1_BASE */
+ ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 1);
+ ptr[i++] = 0x32b;
+ ptr[i++] = 0;
+
+ /* 0xA33A CB_COLOR1_BASE */
+ ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 1);
+ ptr[i++] = 0x33a;
+ ptr[i++] = 0;
+
+ /* SPI_SHADER_COL_FORMAT */
+ ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 1);
+ ptr[i++] = 0x1c5;
+ ptr[i++] = 9;
+
+ /* Setup depth buffer */
+ /* mmDB_Z_INFO */
+ ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 2);
+ ptr[i++] = 0xe;
+ i += 2;
+
+ return i;
+}
+
+static int amdgpu_draw_setup_and_write_drawblt_state(uint32_t *ptr)
+{
+ int i = 0;
+ const uint32_t *cached_cmd_ptr;
+ uint32_t cached_cmd_size;
+
+ /* mmPA_SC_TILE_STEERING_OVERRIDE */
+ ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 1);
+ ptr[i++] = 0xd7;
+ ptr[i++] = 0;
+
+ ptr[i++] = 0xffff1000;
+ ptr[i++] = 0xc0021000;
+
+ ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 1);
+ ptr[i++] = 0xd7;
+ ptr[i++] = 1;
+
+ /* mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0 */
+ ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 16);
+ ptr[i++] = 0x2fe;
+ i += 16;
+
+ /* mmPA_SC_CENTROID_PRIORITY_0 */
+ ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 2);
+ ptr[i++] = 0x2f5;
+ i += 2;
+
+ cached_cmd_ptr = cached_cmd_gfx9;
+ cached_cmd_size = sizeof(cached_cmd_gfx9);
+
+ memcpy(ptr + i, cached_cmd_ptr, cached_cmd_size);
+ i += cached_cmd_size/sizeof(uint32_t);
+
+ return i;
+}
+
+static int amdgpu_draw_vs_RectPosTexFast_write2hw(uint32_t *ptr, uint64_t shader_addr)
+{
+ int i = 0;
+
+ /* mmPA_CL_VS_OUT_CNTL */
+ ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 1);
+ ptr[i++] = 0x207;
+ ptr[i++] = 0;
+
+ /* mmSPI_SHADER_PGM_RSRC3_VS */
+ ptr[i++] = PACKET3(PKT3_SET_SH_REG, 1);
+ ptr[i++] = 0x46;
+ ptr[i++] = 0xffff;
+
+ /* mmSPI_SHADER_PGM_LO_VS...mmSPI_SHADER_PGM_HI_VS */
+ ptr[i++] = PACKET3(PKT3_SET_SH_REG, 2);
+ ptr[i++] = 0x48;
+ ptr[i++] = shader_addr >> 8;
+ ptr[i++] = shader_addr >> 40;
+
+ /* mmSPI_SHADER_PGM_RSRC1_VS */
+ ptr[i++] = PACKET3(PKT3_SET_SH_REG, 1);
+ ptr[i++] = 0x4a;
+ ptr[i++] = 0xc0081;
+ /* mmSPI_SHADER_PGM_RSRC2_VS */
+ ptr[i++] = PACKET3(PKT3_SET_SH_REG, 1);
+ ptr[i++] = 0x4b;
+ ptr[i++] = 0x18;
+
+ /* mmSPI_VS_OUT_CONFIG */
+ ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 1);
+ ptr[i++] = 0x1b1;
+ ptr[i++] = 2;
+
+ /* mmSPI_SHADER_POS_FORMAT */
+ ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 1);
+ ptr[i++] = 0x1c3;
+ ptr[i++] = 4;
+
+ ptr[i++] = PACKET3(PKT3_SET_SH_REG, 4);
+ ptr[i++] = 0x4c;
+ i += 2;
+ ptr[i++] = 0x42000000;
+ ptr[i++] = 0x42000000;
+
+ ptr[i++] = PACKET3(PKT3_SET_SH_REG, 4);
+ ptr[i++] = 0x50;
+ i += 4;
+
+ ptr[i++] = PACKET3(PKT3_SET_SH_REG, 4);
+ ptr[i++] = 0x54;
+ i += 4;
+
+ return i;
+}
+
+static int amdgpu_draw_ps_write2hw(uint32_t *ptr, uint64_t shader_addr)
+{
+ int i, j;
+ const uint32_t *sh_registers;
+ const uint32_t *context_registers;
+ uint32_t num_sh_reg, num_context_reg;
+
+ sh_registers = (const uint32_t *)ps_const_sh_registers_gfx9;
+ context_registers = (const uint32_t *)ps_const_context_reg_gfx9;
+ num_sh_reg = ps_num_sh_registers_gfx9;
+ num_context_reg = ps_num_context_registers_gfx9;
+
+ i = 0;
+
+ /* 0x2c07 SPI_SHADER_PGM_RSRC3_PS
+ 0x2c08 SPI_SHADER_PGM_LO_PS
+ 0x2c09 SPI_SHADER_PGM_HI_PS */
+ shader_addr += 256 * 9;
+ ptr[i++] = PACKET3(PKT3_SET_SH_REG, 3);
+ ptr[i++] = 0x7;
+ ptr[i++] = 0xffff;
+ ptr[i++] = shader_addr >> 8;
+ ptr[i++] = shader_addr >> 40;
+
+ for (j = 0; j < num_sh_reg; j++) {
+ ptr[i++] = PACKET3(PKT3_SET_SH_REG, 1);
+ ptr[i++] = sh_registers[j * 2] - 0x2c00;
+ ptr[i++] = sh_registers[j * 2 + 1];
+ }
+
+ for (j = 0; j < num_context_reg; j++) {
+ if (context_registers[j * 2] != 0xA1C5) {
+ ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 1);
+ ptr[i++] = context_registers[j * 2] - 0xa000;
+ ptr[i++] = context_registers[j * 2 + 1];
+ }
+
+ if (context_registers[j * 2] == 0xA1B4) {
+ ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 1);
+ ptr[i++] = 0x1b3;
+ ptr[i++] = 2;
+ }
+ }
+
+ return i;
+}
+
+static int amdgpu_draw_draw(uint32_t *ptr)
+{
+ int i = 0;
+
+ /* mmIA_MULTI_VGT_PARAM */
+ ptr[i++] = PACKET3(PACKET3_SET_UCONFIG_REG, 1);
+ ptr[i++] = 0x40000258;
+ ptr[i++] = 0xd00ff;
+
+ /* mmVGT_PRIMITIVE_TYPE */
+ ptr[i++] = PACKET3(PACKET3_SET_UCONFIG_REG, 1);
+ ptr[i++] = 0x10000242;
+ ptr[i++] = 0x11;
+
+ ptr[i++] = PACKET3(PACKET3_DRAW_INDEX_AUTO, 1);
+ ptr[i++] = 3;
+ ptr[i++] = 2;
+
+ return i;
+}
+
+void amdgpu_memset_draw(amdgpu_device_handle device_handle,
+ amdgpu_bo_handle bo_shader_ps,
+ amdgpu_bo_handle bo_shader_vs,
+ uint64_t mc_address_shader_ps,
+ uint64_t mc_address_shader_vs,
+ uint32_t ring_id)
+{
+ amdgpu_context_handle context_handle;
+ amdgpu_bo_handle bo_dst, bo_cmd, resources[4];
+ volatile unsigned char *ptr_dst;
+ uint32_t *ptr_cmd;
+ uint64_t mc_address_dst, mc_address_cmd;
+ amdgpu_va_handle va_dst, va_cmd;
+ int i, r;
+ int bo_dst_size = 16384;
+ int bo_cmd_size = 4096;
+ struct amdgpu_cs_request ibs_request = {0};
+ struct amdgpu_cs_ib_info ib_info = {0};
+ struct amdgpu_cs_fence fence_status = {0};
+ uint32_t expired;
+ amdgpu_bo_list_handle bo_list;
+
+ r = amdgpu_cs_ctx_create(device_handle, &context_handle);
+ CU_ASSERT_EQUAL(r, 0);
+
+ r = amdgpu_bo_alloc_and_map(device_handle, bo_cmd_size, 4096,
+ AMDGPU_GEM_DOMAIN_GTT, 0,
+ &bo_cmd, (void **)&ptr_cmd,
+ &mc_address_cmd, &va_cmd);
+ CU_ASSERT_EQUAL(r, 0);
+
+ r = amdgpu_bo_alloc_and_map(device_handle, bo_dst_size, 4096,
+ AMDGPU_GEM_DOMAIN_VRAM, 0,
+ &bo_dst, (void **)&ptr_dst,
+ &mc_address_dst, &va_dst);
+ CU_ASSERT_EQUAL(r, 0);
+
+ i = 0;
+ i += amdgpu_draw_init(ptr_cmd + i);
+
+ i += amdgpu_draw_setup_and_write_drawblt_surf_info(ptr_cmd + i, mc_address_dst);
+
+ i += amdgpu_draw_setup_and_write_drawblt_state(ptr_cmd + i);
+
+ i += amdgpu_draw_vs_RectPosTexFast_write2hw(ptr_cmd + i, mc_address_shader_vs);
+
+ i += amdgpu_draw_ps_write2hw(ptr_cmd + i, mc_address_shader_ps);
+
+ ptr_cmd[i++] = PACKET3(PKT3_SET_SH_REG, 4);
+ ptr_cmd[i++] = 0xc;
+ ptr_cmd[i++] = 0x33333333;
+ ptr_cmd[i++] = 0x33333333;
+ ptr_cmd[i++] = 0x33333333;
+ ptr_cmd[i++] = 0x33333333;
+
+ i += amdgpu_draw_draw(ptr_cmd + i);
+
+ while (i & 7)
+ ptr_cmd[i++] = 0xffff1000; /* type3 nop packet */
+
+ resources[0] = bo_dst;
+ resources[1] = bo_shader_ps;
+ resources[2] = bo_shader_vs;
+ resources[3] = bo_cmd;
+ r = amdgpu_bo_list_create(device_handle, 3, resources, NULL, &bo_list);
+ CU_ASSERT_EQUAL(r, 0);
+
+ ib_info.ib_mc_address = mc_address_cmd;
+ ib_info.size = i;
+ ibs_request.ip_type = AMDGPU_HW_IP_GFX;
+ ibs_request.ring = ring_id;
+ ibs_request.resources = bo_list;
+ ibs_request.number_of_ibs = 1;
+ ibs_request.ibs = &ib_info;
+ ibs_request.fence_info.handle = NULL;
+
+ /* submit CS */
+ r = amdgpu_cs_submit(context_handle, 0, &ibs_request, 1);
+ CU_ASSERT_EQUAL(r, 0);
+
+ r = amdgpu_bo_list_destroy(bo_list);
+ CU_ASSERT_EQUAL(r, 0);
+
+ fence_status.ip_type = AMDGPU_HW_IP_GFX;
+ fence_status.ip_instance = 0;
+ fence_status.ring = ring_id;
+ fence_status.context = context_handle;
+ fence_status.fence = ibs_request.seq_no;
+
+ /* wait for IB accomplished */
+ r = amdgpu_cs_query_fence_status(&fence_status,
+ AMDGPU_TIMEOUT_INFINITE,
+ 0, &expired);
+ CU_ASSERT_EQUAL(r, 0);
+ CU_ASSERT_EQUAL(expired, true);
+
+ /* verify if memset test result meets with expected */
+ i = 0;
+ while(i < bo_dst_size) {
+ CU_ASSERT_EQUAL(ptr_dst[i++], 0x33);
+ }
+
+ r = amdgpu_bo_unmap_and_free(bo_dst, va_dst, mc_address_dst, bo_dst_size);
+ CU_ASSERT_EQUAL(r, 0);
+
+ r = amdgpu_bo_unmap_and_free(bo_cmd, va_cmd, mc_address_cmd, bo_cmd_size);
+ CU_ASSERT_EQUAL(r, 0);
+
+ r = amdgpu_cs_ctx_free(context_handle);
+ CU_ASSERT_EQUAL(r, 0);
+}
+
+static void amdgpu_memset_draw_test(amdgpu_device_handle device_handle,
+ uint32_t ring)
+{
+ amdgpu_bo_handle bo_shader_ps, bo_shader_vs;
+ void *ptr_shader_ps;
+ void *ptr_shader_vs;
+ uint64_t mc_address_shader_ps, mc_address_shader_vs;
+ amdgpu_va_handle va_shader_ps, va_shader_vs;
+ int r;
+ int bo_shader_size = 4096;
+
+ r = amdgpu_bo_alloc_and_map(device_handle, bo_shader_size, 4096,
+ AMDGPU_GEM_DOMAIN_VRAM, 0,
+ &bo_shader_ps, &ptr_shader_ps,
+ &mc_address_shader_ps, &va_shader_ps);
+ CU_ASSERT_EQUAL(r, 0);
+
+ r = amdgpu_bo_alloc_and_map(device_handle, bo_shader_size, 4096,
+ AMDGPU_GEM_DOMAIN_VRAM, 0,
+ &bo_shader_vs, &ptr_shader_vs,
+ &mc_address_shader_vs, &va_shader_vs);
+ CU_ASSERT_EQUAL(r, 0);
+
+ r = amdgpu_draw_load_ps_shader(ptr_shader_ps, PS_CONST);
+ CU_ASSERT_EQUAL(r, 0);
+
+ r = amdgpu_draw_load_vs_shader(ptr_shader_vs);
+ CU_ASSERT_EQUAL(r, 0);
+
+ amdgpu_memset_draw(device_handle, bo_shader_ps, bo_shader_vs,
+ mc_address_shader_ps, mc_address_shader_vs, ring);
+
+ r = amdgpu_bo_unmap_and_free(bo_shader_ps, va_shader_ps, mc_address_shader_ps, bo_shader_size);
+ CU_ASSERT_EQUAL(r, 0);
+
+ r = amdgpu_bo_unmap_and_free(bo_shader_vs, va_shader_vs, mc_address_shader_vs, bo_shader_size);
+ CU_ASSERT_EQUAL(r, 0);
+}
+
+static void amdgpu_draw_test(void)
+{
+ int r;
+ struct drm_amdgpu_info_hw_ip info;
+ uint32_t ring_id;
+
+ r = amdgpu_query_hw_ip_info(device_handle, AMDGPU_HW_IP_GFX, 0, &info);
+ CU_ASSERT_EQUAL(r, 0);
+
+ for (ring_id = 0; (1 << ring_id) & info.available_rings; ring_id++)
+ amdgpu_memset_draw_test(device_handle, ring_id);
+}
--
2.7.4
More information about the amd-gfx
mailing list