[PATCH] drm/amd/amdgpu: fix incorrect translation about the PCIe MLW info

[Alex Deucher]

On Tue, Mar 19, 2019 at 12:26 AM Chengming Gui <Jack.Gui at amd.com> wrote:
>
> Max Link Width's full mask is 0x3f,
> and it's highest bit express X16.
>
> Signed-off-by: Chengming Gui <Jack.Gui at amd.com>
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 12 ++----------
>  1 file changed, 2 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> index 964a4d3..435f0d7 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> @@ -3763,15 +3763,6 @@ static void amdgpu_device_get_pcie_info(struct amdgpu_device *adev)
>                 } else {
>                         switch (platform_link_width) {
>                         case PCIE_LNK_X32:
> -                               adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X32 |
> -                                                         CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 |
> -                                                         CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
> -                                                         CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
> -                                                         CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
> -                                                         CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
> -                                                         CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
> -                               break;
> -                       case PCIE_LNK_X16:
>                                 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 |
>                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
>                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
> @@ -3779,13 +3770,14 @@ static void amdgpu_device_get_pcie_info(struct amdgpu_device *adev)
>                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
>                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
>                                 break;
> -                       case PCIE_LNK_X12:
> +                       case PCIE_LNK_X16:

Not sure I understand this change or the one below.  If we have a x16
link, why don't you want CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 set?

Alex

>                                 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
>                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
>                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
>                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
>                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
>                                 break;
> +                       case PCIE_LNK_X12:
>                         case PCIE_LNK_X8:
>                                 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
>                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
> --
> 2.7.4
>
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