AMD Freesync patches v3

[Mario Kleiner]

The hopefully final patch series, with feedback applied and
r-b / acked-by tags added. Rebased to current agd5f/drm-5.2-wip
branch.

Numbering has slightly changed. Patches 3-5 are identical to last
series. Patch 2/5 v3 (the former 1/4 v2) trivially rebased on top of
the new 1/5.

Patch 1/5 is new and splits the VRR state updating to a part
early in commit_tail, before the vrr transition handling from
Patch 2/5, and a late part in the plane commit code, which must
happen after transition handling/during plane commit.

This should address all of Nicholas remaining comments. Tested
and nicely working on DCN-1.0 / Raven as well.

Thanks,
-mario