[PATCH 5/9] drm/amdgpu: call psp to progrm ih cntl in SR-IOV
Alex Deucher
alexdeucher at gmail.com
Thu May 9 05:50:38 UTC 2019
On Tue, May 7, 2019 at 10:46 PM Trigger Huang <Trigger.Huang at amd.com> wrote:
>
> call psp to progrm ih cntl in SR-IOV if supported
typo in subject and description:
progrm -> program
With that fixed:
Reviewed-by: Alex Deucher <alexander.deucher at amd.com>
>
> Change-Id: I466dd66926221e764cbcddca48b1f0fe5cd798b4
> Signed-off-by: Trigger Huang <Trigger.Huang at amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/vega10_ih.c | 91 ++++++++++++++++++++++++++++++----
> 1 file changed, 82 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
> index 1b2f69a..fbb1ed8 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
> @@ -48,14 +48,29 @@ static void vega10_ih_enable_interrupts(struct amdgpu_device *adev)
>
> ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 1);
> ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 1);
> - WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl);
> + if (amdgpu_virt_support_psp_prg_ih_reg(adev)) {
> + if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL, ih_rb_cntl)) {
> + DRM_ERROR("PSP program IH_RB_CNTL failed!\n");
> + return;
> + }
> + } else {
> + WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl);
> + }
> adev->irq.ih.enabled = true;
>
> if (adev->irq.ih1.ring_size) {
> ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1);
> ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING1,
> RB_ENABLE, 1);
> - WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl);
> + if (amdgpu_virt_support_psp_prg_ih_reg(adev)) {
> + if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING1,
> + ih_rb_cntl)) {
> + DRM_ERROR("program IH_RB_CNTL_RING1 failed!\n");
> + return;
> + }
> + } else {
> + WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl);
> + }
> adev->irq.ih1.enabled = true;
> }
>
> @@ -63,7 +78,15 @@ static void vega10_ih_enable_interrupts(struct amdgpu_device *adev)
> ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2);
> ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING2,
> RB_ENABLE, 1);
> - WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl);
> + if (amdgpu_virt_support_psp_prg_ih_reg(adev)) {
> + if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING2,
> + ih_rb_cntl)) {
> + DRM_ERROR("program IH_RB_CNTL_RING2 failed!\n");
> + return;
> + }
> + } else {
> + WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl);
> + }
> adev->irq.ih2.enabled = true;
> }
> }
> @@ -81,7 +104,15 @@ static void vega10_ih_disable_interrupts(struct amdgpu_device *adev)
>
> ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 0);
> ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 0);
> - WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl);
> + if (amdgpu_virt_support_psp_prg_ih_reg(adev)) {
> + if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL, ih_rb_cntl)) {
> + DRM_ERROR("PSP program IH_RB_CNTL failed!\n");
> + return;
> + }
> + } else {
> + WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl);
> + }
> +
> /* set rptr, wptr to 0 */
> WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR, 0);
> WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR, 0);
> @@ -92,7 +123,15 @@ static void vega10_ih_disable_interrupts(struct amdgpu_device *adev)
> ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1);
> ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING1,
> RB_ENABLE, 0);
> - WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl);
> + if (amdgpu_virt_support_psp_prg_ih_reg(adev)) {
> + if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING1,
> + ih_rb_cntl)) {
> + DRM_ERROR("program IH_RB_CNTL_RING1 failed!\n");
> + return;
> + }
> + } else {
> + WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl);
> + }
> /* set rptr, wptr to 0 */
> WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING1, 0);
> WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_RING1, 0);
> @@ -104,7 +143,16 @@ static void vega10_ih_disable_interrupts(struct amdgpu_device *adev)
> ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2);
> ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING2,
> RB_ENABLE, 0);
> - WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl);
> + if (amdgpu_virt_support_psp_prg_ih_reg(adev)) {
> + if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING2,
> + ih_rb_cntl)) {
> + DRM_ERROR("program IH_RB_CNTL_RING2 failed!\n");
> + return;
> + }
> + } else {
> + WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl);
> + }
> +
> /* set rptr, wptr to 0 */
> WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING2, 0);
> WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_RING2, 0);
> @@ -187,7 +235,15 @@ static int vega10_ih_irq_init(struct amdgpu_device *adev)
> ih_rb_cntl = vega10_ih_rb_cntl(ih, ih_rb_cntl);
> ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RPTR_REARM,
> !!adev->irq.msi_enabled);
> - WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl);
> +
> + if (amdgpu_virt_support_psp_prg_ih_reg(adev)) {
> + if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL, ih_rb_cntl)) {
> + DRM_ERROR("PSP program IH_RB_CNTL failed!\n");
> + return -ETIMEDOUT;
> + }
> + } else {
> + WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl);
> + }
>
> /* set the writeback address whether it's enabled or not */
> WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_ADDR_LO,
> @@ -214,7 +270,15 @@ static int vega10_ih_irq_init(struct amdgpu_device *adev)
> WPTR_OVERFLOW_ENABLE, 0);
> ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,
> RB_FULL_DRAIN_ENABLE, 1);
> - WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl);
> + if (amdgpu_virt_support_psp_prg_ih_reg(adev)) {
> + if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING1,
> + ih_rb_cntl)) {
> + DRM_ERROR("program IH_RB_CNTL_RING1 failed!\n");
> + return -ETIMEDOUT;
> + }
> + } else {
> + WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl);
> + }
>
> /* set rptr, wptr to 0 */
> WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_RING1, 0);
> @@ -232,7 +296,16 @@ static int vega10_ih_irq_init(struct amdgpu_device *adev)
>
> ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2);
> ih_rb_cntl = vega10_ih_rb_cntl(ih, ih_rb_cntl);
> - WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl);
> +
> + if (amdgpu_virt_support_psp_prg_ih_reg(adev)) {
> + if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING2,
> + ih_rb_cntl)) {
> + DRM_ERROR("program IH_RB_CNTL_RING2 failed!\n");
> + return -ETIMEDOUT;
> + }
> + } else {
> + WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl);
> + }
>
> /* set rptr, wptr to 0 */
> WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_RING2, 0);
> --
> 2.7.4
>
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