[PATCH] drm/amdgpu: no read DF register under SRIOV and set correct vram width

[Yintian Tao]

PART1:
Under SRIOV, reading DF register has chance to lead to
AER error in host side, just skip reading it.
PART2:
For Vega10 SR-IOV, vram_width can't be read from ATOM as
RAVEN, and DF related registers is not readable, seems hardcord
is the only way to set the correct vram_width.

Signed-off-by: Trigger Huang <Trigger.Huang at amd.com>
Signed-off-by: Monk Liu <Monk.Liu at amd.com>
Signed-off-by: Yintian Tao <yttao at amd.com>
---
 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index c221570..b5bf9ed 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -837,7 +837,7 @@ static int gmc_v9_0_mc_init(struct amdgpu_device *adev)
 
 	if (amdgpu_emu_mode != 1)
 		adev->gmc.vram_width = amdgpu_atomfirmware_get_vram_width(adev);
-	if (!adev->gmc.vram_width) {
+	if (!adev->gmc.vram_width && !amdgpu_sriov_vf(adev)) {
 		/* hbm memory channel size */
 		if (adev->flags & AMD_IS_APU)
 			chansize = 64;
@@ -848,6 +848,13 @@ static int gmc_v9_0_mc_init(struct amdgpu_device *adev)
 		adev->gmc.vram_width = numchan * chansize;
 	}
 
+	/* For Vega10 SR-IOV, vram_width can't be read from ATOM as RAVEN,
+	 * and DF related registers is not readable, seems hardcord is the
+	 * only way to set the correct vram_width */
+	if (amdgpu_sriov_vf(adev) && (adev->asic_type == CHIP_VEGA10)) {
+		adev->gmc.vram_width = 2048;
+	}
+
 	/* size in MB on si */
 	adev->gmc.mc_vram_size =
 		adev->nbio_funcs->get_memsize(adev) * 1024ULL * 1024ULL;
-- 
2.7.4