[PATCH 1/2] Revert "drm/amdgpu: don't read registers if gfxoff is enabled (v2)"

[Alex Deucher]

This reverts commit 5e49d6f654c569c2de920babbaf5cf7c4c4a353f.

Drop this workaround in favor of a better one.

Signed-off-by: Alex Deucher <alexander.deucher at amd.com>
---
 drivers/gpu/drm/amd/amdgpu/nv.c    | 27 ++++++++++----------------
 drivers/gpu/drm/amd/amdgpu/soc15.c | 31 ++++++++++++------------------
 2 files changed, 22 insertions(+), 36 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
index 7283d6198b89..af68f9815f28 100644
--- a/drivers/gpu/drm/amd/amdgpu/nv.c
+++ b/drivers/gpu/drm/amd/amdgpu/nv.c
@@ -201,25 +201,17 @@ static uint32_t nv_read_indexed_register(struct amdgpu_device *adev, u32 se_num,
 	return val;
 }
 
-static int nv_get_register_value(struct amdgpu_device *adev,
+static uint32_t nv_get_register_value(struct amdgpu_device *adev,
 				      bool indexed, u32 se_num,
-				      u32 sh_num, u32 reg_offset,
-				      u32 *value)
+				      u32 sh_num, u32 reg_offset)
 {
 	if (indexed) {
-		if (adev->pm.pp_feature & PP_GFXOFF_MASK)
-			return -EINVAL;
-		*value = nv_read_indexed_register(adev, se_num, sh_num, reg_offset);
+		return nv_read_indexed_register(adev, se_num, sh_num, reg_offset);
 	} else {
-		if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG)) {
-			*value = adev->gfx.config.gb_addr_config;
-		} else {
-			if (adev->pm.pp_feature & PP_GFXOFF_MASK)
-				return -EINVAL;
-			*value = RREG32(reg_offset);
-		}
+		if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG))
+			return adev->gfx.config.gb_addr_config;
+		return RREG32(reg_offset);
 	}
-	return 0;
 }
 
 static int nv_read_register(struct amdgpu_device *adev, u32 se_num,
@@ -235,9 +227,10 @@ static int nv_read_register(struct amdgpu_device *adev, u32 se_num,
 		    (adev->reg_offset[en->hwip][en->inst][en->seg] + en->reg_offset))
 			continue;
 
-		return nv_get_register_value(adev,
-					     nv_allowed_read_registers[i].grbm_indexed,
-					     se_num, sh_num, reg_offset, value);
+		*value = nv_get_register_value(adev,
+					       nv_allowed_read_registers[i].grbm_indexed,
+					       se_num, sh_num, reg_offset);
+		return 0;
 	}
 	return -EINVAL;
 }
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
index 3b55655f79c4..8e1640bc07af 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -363,27 +363,19 @@ static uint32_t soc15_read_indexed_register(struct amdgpu_device *adev, u32 se_n
 	return val;
 }
 
-static int soc15_get_register_value(struct amdgpu_device *adev,
+static uint32_t soc15_get_register_value(struct amdgpu_device *adev,
 					 bool indexed, u32 se_num,
-					 u32 sh_num, u32 reg_offset,
-					 u32 *value)
+					 u32 sh_num, u32 reg_offset)
 {
 	if (indexed) {
-		if (adev->pm.pp_feature & PP_GFXOFF_MASK)
-			return -EINVAL;
-	        *value = soc15_read_indexed_register(adev, se_num, sh_num, reg_offset);
+		return soc15_read_indexed_register(adev, se_num, sh_num, reg_offset);
 	} else {
-		if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG)) {
-			*value = adev->gfx.config.gb_addr_config;
-		} else if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmDB_DEBUG2)) {
-			*value = adev->gfx.config.db_debug2;
-		} else {
-			if (adev->pm.pp_feature & PP_GFXOFF_MASK)
-				return -EINVAL;
-			*value = RREG32(reg_offset);
-		}
+		if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG))
+			return adev->gfx.config.gb_addr_config;
+		else if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmDB_DEBUG2))
+			return adev->gfx.config.db_debug2;
+		return RREG32(reg_offset);
 	}
-	return 0;
 }
 
 static int soc15_read_register(struct amdgpu_device *adev, u32 se_num,
@@ -399,9 +391,10 @@ static int soc15_read_register(struct amdgpu_device *adev, u32 se_num,
 					+ en->reg_offset))
 			continue;
 
-		return soc15_get_register_value(adev,
-						soc15_allowed_read_registers[i].grbm_indexed,
-						se_num, sh_num, reg_offset, value);
+		*value = soc15_get_register_value(adev,
+						  soc15_allowed_read_registers[i].grbm_indexed,
+						  se_num, sh_num, reg_offset);
+		return 0;
 	}
 	return -EINVAL;
 }
-- 
2.23.0