[PATCH 1/2] drm/dsc: Update drm_dsc to reflect native 4.2.0 DSC spec

[Harry Wentland]

On 2019-11-14 4:20 p.m., Cornij, Nikola wrote:
> This looks good, too.
> 

Can we treat this as your reviewed-by for both changes?

Usually people mark these as reviewed with a
Reviewed-by: Harry Wentland <harry.wentland at amd.com>

Thanks,
Harry

> -----Original Message-----
> From: mikita.lipski at amd.com <mikita.lipski at amd.com> 
> Sent: November 13, 2019 2:07 PM
> To: amd-gfx at lists.freedesktop.org
> Cc: Wentland, Harry <Harry.Wentland at amd.com>; Deucher, Alexander <Alexander.Deucher at amd.com>; Cornij, Nikola <Nikola.Cornij at amd.com>; manasi.d.navare at intel.com; Lipski, Mikita <Mikita.Lipski at amd.com>; David Francis <David.Francis at amd.com>
> Subject: [PATCH 1/2] drm/dsc: Update drm_dsc to reflect native 4.2.0 DSC spec
> 
> From: Mikita Lipski <mikita.lipski at amd.com>
> 
> [Why]
> Some parts of the DSC spec relating to 4.2.0 were not reflected in drm_dsc_compute_rc_parameters, causing unexpected config failures
> 
> [How]
> Add nsl_bpg_offset and rbs_min computation
> 
> Signed-off-by: David Francis <David.Francis at amd.com>
> Signed-off-by: Mikita Lipski <mikita.lipski at amd.com>
> ---
>  drivers/gpu/drm/drm_dsc.c | 72 ++++++++++++++++++++++++++++++++++++---
>  1 file changed, 68 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/drm_dsc.c b/drivers/gpu/drm/drm_dsc.c index 77f4e5ae4197..79c71e3fc973 100644
> --- a/drivers/gpu/drm/drm_dsc.c
> +++ b/drivers/gpu/drm/drm_dsc.c
> @@ -245,6 +245,38 @@ void drm_dsc_pps_payload_pack(struct drm_dsc_picture_parameter_set *pps_payload,  }  EXPORT_SYMBOL(drm_dsc_pps_payload_pack);
>  
> +static int compute_offset(struct drm_dsc_config *vdsc_cfg, int pixels_per_group,
> +				int groups_per_line, int grpcnt)
> +{
> +	int offset = 0;
> +	int grpcnt_id = DIV_ROUND_UP(vdsc_cfg->initial_xmit_delay, 
> +pixels_per_group);
> +
> +	if (grpcnt <= grpcnt_id)
> +		offset = DIV_ROUND_UP(grpcnt * pixels_per_group * vdsc_cfg->bits_per_pixel, 16);
> +	else
> +		offset = DIV_ROUND_UP(grpcnt_id * pixels_per_group * vdsc_cfg->bits_per_pixel, 16)
> +			- (((grpcnt - grpcnt_id) * vdsc_cfg->slice_bpg_offset) >> 11);
> +
> +	if (grpcnt <= groups_per_line)
> +		offset += grpcnt * vdsc_cfg->first_line_bpg_offset;
> +	else
> +		offset += groups_per_line * vdsc_cfg->first_line_bpg_offset
> +			- (((grpcnt - groups_per_line) * vdsc_cfg->nfl_bpg_offset) >> 11);
> +
> +	if (vdsc_cfg->native_420) {
> +		if (grpcnt <= groups_per_line)
> +			offset -= (grpcnt * vdsc_cfg->nsl_bpg_offset) >> 11;
> +		else if (grpcnt <= 2 * groups_per_line)
> +			offset += (grpcnt - groups_per_line) * vdsc_cfg->second_line_bpg_offset
> +				- ((groups_per_line * vdsc_cfg->nsl_bpg_offset) >> 11);
> +		else
> +			offset += (grpcnt - groups_per_line) * vdsc_cfg->second_line_bpg_offset
> +				- (((grpcnt - groups_per_line) * vdsc_cfg->nsl_bpg_offset) >> 11);
> +	}
> +
> +	return offset;
> +}
> +
>  /**
>   * drm_dsc_compute_rc_parameters() - Write rate control
>   * parameters to the dsc configuration defined in @@ -264,6 +296,7 @@ int drm_dsc_compute_rc_parameters(struct drm_dsc_config *vdsc_cfg)
>  	unsigned long hrd_delay = 0;
>  	unsigned long final_scale = 0;
>  	unsigned long rbs_min = 0;
> +	unsigned long max_offset = 0;
>  
>  	if (vdsc_cfg->native_420 || vdsc_cfg->native_422) {
>  		/* Number of groups used to code each line of a slice */ @@ -342,6 +375,17 @@ int drm_dsc_compute_rc_parameters(struct drm_dsc_config *vdsc_cfg)
>  		return -ERANGE;
>  	}
>  
> +	if (vdsc_cfg->slice_height > 2)
> +		vdsc_cfg->nsl_bpg_offset = DIV_ROUND_UP((vdsc_cfg->second_line_bpg_offset << 11),
> +							(vdsc_cfg->slice_height - 1));
> +	else
> +		vdsc_cfg->nsl_bpg_offset = 0;
> +
> +	if (vdsc_cfg->nsl_bpg_offset > 65535) {
> +		DRM_DEBUG_KMS("NslBpgOffset is too large for this slice height\n");
> +		return -ERANGE;
> +	}
> +
>  	/* Number of groups used to code the entire slice */
>  	groups_total = groups_per_line * vdsc_cfg->slice_height;
>  
> @@ -361,6 +405,7 @@ int drm_dsc_compute_rc_parameters(struct drm_dsc_config *vdsc_cfg)
>  		vdsc_cfg->scale_increment_interval =
>  				(vdsc_cfg->final_offset * (1 << 11)) /
>  				((vdsc_cfg->nfl_bpg_offset +
> +				vdsc_cfg->nsl_bpg_offset +
>  				vdsc_cfg->slice_bpg_offset) *
>  				(final_scale - 9));
>  	} else {
> @@ -381,10 +426,29 @@ int drm_dsc_compute_rc_parameters(struct drm_dsc_config *vdsc_cfg)
>  	 * bits/pixel (bpp) rate that is used by the encoder,
>  	 * in steps of 1/16 of a bit per pixel
>  	 */
> -	rbs_min = vdsc_cfg->rc_model_size - vdsc_cfg->initial_offset +
> -		DIV_ROUND_UP(vdsc_cfg->initial_xmit_delay *
> -			     vdsc_cfg->bits_per_pixel, 16) +
> -		groups_per_line * vdsc_cfg->first_line_bpg_offset;
> +	if (vdsc_cfg->dsc_version_minor == 2 && (vdsc_cfg->native_420 || 
> +vdsc_cfg->native_422)) {
> +
> +		max_offset = compute_offset(vdsc_cfg, DSC_RC_PIXELS_PER_GROUP, groups_per_line,
> +					DIV_ROUND_UP(vdsc_cfg->initial_xmit_delay,
> +						DSC_RC_PIXELS_PER_GROUP));
> +
> +		max_offset = max(max_offset,
> +				compute_offset(vdsc_cfg, DSC_RC_PIXELS_PER_GROUP, groups_per_line,
> +					DIV_ROUND_UP(vdsc_cfg->initial_xmit_delay,
> +						groups_per_line)));
> +
> +		max_offset = max(max_offset,
> +				compute_offset(vdsc_cfg, DSC_RC_PIXELS_PER_GROUP, groups_per_line,
> +					DIV_ROUND_UP(vdsc_cfg->initial_xmit_delay,
> +						groups_per_line * 2)));
> +
> +		rbs_min = vdsc_cfg->rc_model_size - vdsc_cfg->initial_offset + max_offset;
> +	} else {
> +		rbs_min = vdsc_cfg->rc_model_size - vdsc_cfg->initial_offset +
> +			DIV_ROUND_UP(vdsc_cfg->initial_xmit_delay *
> +				     vdsc_cfg->bits_per_pixel, 16) +
> +			groups_per_line * vdsc_cfg->first_line_bpg_offset;
> +	}
>  
>  	hrd_delay = DIV_ROUND_UP((rbs_min * 16), vdsc_cfg->bits_per_pixel);
>  	vdsc_cfg->rc_bits = (hrd_delay * vdsc_cfg->bits_per_pixel) / 16;
> --
> 2.17.1
>