[PATCH v2 0/3] RAS support for mmhub

[Zhang, Hawking]

Series is

Reviewed-by: Hawking Zhang <Hawking.Zhang at amd.com>

Regards,
Hawking
-----Original Message-----
From: Dennis Li <Dennis.Li at amd.com> 
Sent: 2019年11月20日 18:49
To: amd-gfx at lists.freedesktop.org; Deucher, Alexander <Alexander.Deucher at amd.com>; Zhou1, Tao <Tao.Zhou1 at amd.com>; Zhang, Hawking <Hawking.Zhang at amd.com>; Chen, Guchun <Guchun.Chen at amd.com>
Cc: Li, Dennis <Dennis.Li at amd.com>
Subject: [PATCH v2 0/3] RAS support for mmhub

This set of patches is a continuation of RAS enablement patches for AMDGPU. 

1. The new struct soc15_ras_field_entry will be reused by gfx, mmhub and other IP blocks.
2. Refine the query function of RAS error counter for VG20, add codes to help user to locate which sub-block of mmhub cause error.
3. Implement the query function of RAS error counter for Mi100

v2:
1. Fix some comment issues.
2. Add IP name prefix for the local static variable and function.
3. Move the EDC_CNT registers' defintion from mmhub_9_4 header files to mmhub_1_0 ones for vg20.

Dennis Li (3):
  drm/amdgpu: define soc15_ras_field_entry for reuse
  drm/amdgpu: refine query function of mmhub EDC counter in vg20
  drm/amdgpu: implement querying ras error count for mmhub9.4

 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c         |  34 +--
 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c         |   3 +
 drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c       | 232 ++++++++++++----
 drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c       | 253 ++++++++++++++++-
 drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.h       |   2 +
 drivers/gpu/drm/amd/amdgpu/soc15.h            |  12 +
 .../include/asic_reg/mmhub/mmhub_1_0_offset.h |  16 ++
 .../asic_reg/mmhub/mmhub_1_0_sh_mask.h        | 122 +++++++++
 .../asic_reg/mmhub/mmhub_9_4_0_offset.h       |  53 ----
 .../asic_reg/mmhub/mmhub_9_4_0_sh_mask.h      | 257 ------------------
 10 files changed, 598 insertions(+), 386 deletions(-)  delete mode 100644 drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_9_4_0_offset.h
 delete mode 100644 drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_9_4_0_sh_mask.h

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2.17.1