[PATCH v2 1/3] drm/amdgpu: define soc15_ras_field_entry for reuse

[Deucher, Alexander]

Series is:
Reviewed-by: Alex Deucher <alexander.deucher at amd.com>
________________________________
From: Dennis Li <Dennis.Li at amd.com>
Sent: Wednesday, November 20, 2019 5:49 AM
To: amd-gfx at lists.freedesktop.org <amd-gfx at lists.freedesktop.org>; Deucher, Alexander <Alexander.Deucher at amd.com>; Zhou1, Tao <Tao.Zhou1 at amd.com>; Zhang, Hawking <Hawking.Zhang at amd.com>; Chen, Guchun <Guchun.Chen at amd.com>
Cc: Li, Dennis <Dennis.Li at amd.com>; Li, Dennis <Dennis.Li at amd.com>
Subject: [PATCH v2 1/3] drm/amdgpu: define soc15_ras_field_entry for reuse

The struct soc15_ras_field_entry will be reused by
other IPs, such as mmhub and gc

v2: rename ras_subblock_regs to gc_ras_fields_vg20,
because the future asic maybe have a different table.

Change-Id: I6c3388a09b5fbf927ad90fcd626baa448d1681a6
Signed-off-by: Dennis Li <dennis.li at amd.com>
---
 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 34 +++++++++------------------
 drivers/gpu/drm/amd/amdgpu/soc15.h    | 12 ++++++++++
 2 files changed, 23 insertions(+), 23 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index c7ae685d6f74..8073fcd4720e 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -131,18 +131,6 @@ MODULE_FIRMWARE("amdgpu/renoir_rlc.bin");
 #define mmTCP_CHAN_STEER_5_ARCT                                                         0x0b0c
 #define mmTCP_CHAN_STEER_5_ARCT_BASE_IDX                                                        0

-struct ras_gfx_subblock_reg {
-       const char *name;
-       uint32_t hwip;
-       uint32_t inst;
-       uint32_t seg;
-       uint32_t reg_offset;
-       uint32_t sec_count_mask;
-       uint32_t sec_count_shift;
-       uint32_t ded_count_mask;
-       uint32_t ded_count_shift;
-};
-
 enum ta_ras_gfx_subblock {
         /*CPC*/
         TA_RAS_BLOCK__GFX_CPC_INDEX_START = 0,
@@ -5487,7 +5475,7 @@ static int gfx_v9_0_priv_inst_irq(struct amdgpu_device *adev,
 }


-static const struct ras_gfx_subblock_reg ras_subblock_regs[] = {
+static const struct soc15_ras_field_entry gc_ras_fields_vg20[] = {
         { "CPC_SCRATCH", SOC15_REG_ENTRY(GC, 0, mmCPC_EDC_SCRATCH_CNT),
           SOC15_REG_FIELD(CPC_EDC_SCRATCH_CNT, SEC_COUNT),
           SOC15_REG_FIELD(CPC_EDC_SCRATCH_CNT, DED_COUNT)
@@ -6146,29 +6134,29 @@ static int __get_ras_error_count(const struct soc15_reg_entry *reg,
         uint32_t i;
         uint32_t sec_cnt, ded_cnt;

-       for (i = 0; i < ARRAY_SIZE(ras_subblock_regs); i++) {
-               if(ras_subblock_regs[i].reg_offset != reg->reg_offset ||
-                       ras_subblock_regs[i].seg != reg->seg ||
-                       ras_subblock_regs[i].inst != reg->inst)
+       for (i = 0; i < ARRAY_SIZE(gc_ras_fields_vg20); i++) {
+               if(gc_ras_fields_vg20[i].reg_offset != reg->reg_offset ||
+                       gc_ras_fields_vg20[i].seg != reg->seg ||
+                       gc_ras_fields_vg20[i].inst != reg->inst)
                         continue;

                 sec_cnt = (value &
-                               ras_subblock_regs[i].sec_count_mask) >>
-                               ras_subblock_regs[i].sec_count_shift;
+                               gc_ras_fields_vg20[i].sec_count_mask) >>
+                               gc_ras_fields_vg20[i].sec_count_shift;
                 if (sec_cnt) {
                         DRM_INFO("GFX SubBlock %s, Instance[%d][%d], SEC %d\n",
-                               ras_subblock_regs[i].name,
+                               gc_ras_fields_vg20[i].name,
                                 se_id, inst_id,
                                 sec_cnt);
                         *sec_count += sec_cnt;
                 }

                 ded_cnt = (value &
-                               ras_subblock_regs[i].ded_count_mask) >>
-                               ras_subblock_regs[i].ded_count_shift;
+                               gc_ras_fields_vg20[i].ded_count_mask) >>
+                               gc_ras_fields_vg20[i].ded_count_shift;
                 if (ded_cnt) {
                         DRM_INFO("GFX SubBlock %s, Instance[%d][%d], DED %d\n",
-                               ras_subblock_regs[i].name,
+                               gc_ras_fields_vg20[i].name,
                                 se_id, inst_id,
                                 ded_cnt);
                         *ded_count += ded_cnt;
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.h b/drivers/gpu/drm/amd/amdgpu/soc15.h
index 9af6c6ffbfa2..344280b869c4 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.h
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.h
@@ -60,6 +60,18 @@ struct soc15_allowed_register_entry {
         bool grbm_indexed;
 };

+struct soc15_ras_field_entry {
+       const char *name;
+       uint32_t hwip;
+       uint32_t inst;
+       uint32_t seg;
+       uint32_t reg_offset;
+       uint32_t sec_count_mask;
+       uint32_t sec_count_shift;
+       uint32_t ded_count_mask;
+       uint32_t ded_count_shift;
+};
+
 #define SOC15_REG_ENTRY(ip, inst, reg)  ip##_HWIP, inst, reg##_BASE_IDX, reg

 #define SOC15_REG_ENTRY_OFFSET(entry)   (adev->reg_offset[entry.hwip][entry.inst][entry.seg] + entry.reg_offset)
--
2.17.1

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