[PATCH 11/38] drm/amd/display: Add missing shifts and masks for dpp registers on dcn2

[Bhawanpreet Lakha]

From: Joshua Aberback <joshua.aberback at amd.com>

[Why]
The register CM_TEST_DEBUG_DATA is used in dpp1_program_input_csc, which is
called from dpp2_cnv_setup, but the shifts and masks for the fields of that
register are not initialized for dcn2. This causes all reads of that register
to return 0.

Change-Id: I89d7c29153e14947b97bfee7d3b74c0814d7aa25
Signed-off-by: Joshua Aberback <joshua.aberback at amd.com>
Reviewed-by: Jaehyun Chung <Jaehyun.Chung at amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha at amd.com>
---
 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
index af0e0d1be147..13484fff7ad6 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
@@ -581,11 +581,13 @@ static const struct dcn2_dpp_registers tf_regs[] = {
 };
 
 static const struct dcn2_dpp_shift tf_shift = {
-		TF_REG_LIST_SH_MASK_DCN20(__SHIFT)
+		TF_REG_LIST_SH_MASK_DCN20(__SHIFT),
+		TF_DEBUG_REG_LIST_SH_DCN10
 };
 
 static const struct dcn2_dpp_mask tf_mask = {
-		TF_REG_LIST_SH_MASK_DCN20(_MASK)
+		TF_REG_LIST_SH_MASK_DCN20(_MASK),
+		TF_DEBUG_REG_LIST_MASK_DCN10
 };
 
 #define dwbc_regs_dcn2(id)\
-- 
2.17.1