[PATCH 2/2] drm/amdgpu: disable MSI-X on APUs

[Liu, Shaoyun]

Thanks Alex and  Tom to catch and  revolve the issue .  I didn't do 
enough test on original test.

We don't need to enable msix  on APU .   The serials is reviewed by 
shaoyun.liu <shaoyun.liu at amd.com>


Regards

shaoyun.liu



On 2019-10-03 10:13 a.m., Alex Deucher wrote:
> Raven claims to support them, but seems to have problems.  Stick
> with MSIs for now on APUs.
>
> Tested-by: Tom St Denis <tom.stdenis at amd.com>
> Signed-off-by: Alex Deucher <alexander.deucher at amd.com>
> ---
>   drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c | 3 ++-
>   1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
> index 98aa28edba6a..8f2236bd7d0e 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
> @@ -248,7 +248,8 @@ int amdgpu_irq_init(struct amdgpu_device *adev)
>   		unsigned int flags;
>   		int nvec = pci_msix_vec_count(adev->pdev);
>   
> -		if (nvec <= 0) {
> +		/* Raven claims to support MSI-X, but seems to have problems */
> +		if ((nvec <= 0) || (adev->flags & AMD_IS_APU)) {
>   			flags = PCI_IRQ_MSI;
>   			nvec = 1;
>   		} else {