[PATCH] drm/amd/display: add NULL checks for clock manager pointer

Harry Wentland hwentlan at amd.com
Tue Oct 15 14:06:18 UTC 2019


On 2019-10-11 4:51 p.m., Alex Deucher wrote:
> From: Ahzo <Ahzo at tutanota.com>
> 
> This fixes kernel NULL pointer dereferences on shutdown:
> RIP: 0010:build_audio_output.isra.0+0x97/0x110 [amdgpu]
> RIP: 0010:enable_link_dp+0x186/0x300 [amdgpu]
> 
> Signed-off-by: Ahzo <Ahzo at tutanota.com>
> Signed-off-by: Alex Deucher <alexander.deucher at amd.com>

Reviewed-by: Harry Wentland <harry.wentland at amd.com>

Harry

> ---
>  drivers/gpu/drm/amd/display/dc/core/dc_link.c               | 2 +-
>  drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c | 5 +++--
>  2 files changed, 4 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
> index 152c564a8344..8b58cfa3e98e 100644
> --- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
> +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
> @@ -1510,7 +1510,7 @@ static enum dc_status enable_link_dp(
>  
>  	pipe_ctx->stream_res.pix_clk_params.requested_sym_clk =
>  			link_settings.link_rate * LINK_RATE_REF_FREQ_IN_KHZ;
> -	if (!apply_seamless_boot_optimization)
> +	if (state->clk_mgr && !apply_seamless_boot_optimization)
>  		state->clk_mgr->funcs->update_clocks(state->clk_mgr, state, false);
>  
>  	dp_enable_link_phy(
> diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
> index f8c1b4f1b987..8d8fa10b5d86 100644
> --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
> +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
> @@ -1161,8 +1161,9 @@ static void build_audio_output(
>  		}
>  	}
>  
> -	if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT ||
> -			pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
> +	if (state->clk_mgr &&
> +		(pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT ||
> +			pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)) {
>  		audio_output->pll_info.dp_dto_source_clock_in_khz =
>  				state->clk_mgr->funcs->get_dp_ref_clk_frequency(
>  						state->clk_mgr);
> 


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