[PATCH] drm/amdgpu/gmc10: properly set BANK_SELECT and FRAGMENT_SIZE

[Christian König]

Am 29.10.19 um 22:15 schrieb Alex Deucher:
> These were not aligned for optimal performance for GPUVM.
>
> Signed-off-by: Alex Deucher <alexander.deucher at amd.com>

Good catch. But I haven't read the GMC10 documentation yet of everything 
is still the same as on GMC9.

So only Acked-by: Christian König <christian.koenig at amd.com>

Regards,
Christian.

> ---
>   drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c | 9 +++++++++
>   drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c  | 9 +++++++++
>   2 files changed, 18 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c b/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c
> index b601c6740ef5..b4f32d853ca1 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c
> @@ -155,6 +155,15 @@ static void gfxhub_v2_0_init_cache_regs(struct amdgpu_device *adev)
>   	WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL2, tmp);
>   
>   	tmp = mmGCVM_L2_CNTL3_DEFAULT;
> +	if (adev->gmc.translate_further) {
> +		tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, BANK_SELECT, 12);
> +		tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3,
> +				    L2_CACHE_BIGK_FRAGMENT_SIZE, 9);
> +	} else {
> +		tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, BANK_SELECT, 9);
> +		tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3,
> +				    L2_CACHE_BIGK_FRAGMENT_SIZE, 6);
> +	}
>   	WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL3, tmp);
>   
>   	tmp = mmGCVM_L2_CNTL4_DEFAULT;
> diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c
> index 2eea702de8ee..945533634711 100644
> --- a/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c
> @@ -142,6 +142,15 @@ static void mmhub_v2_0_init_cache_regs(struct amdgpu_device *adev)
>   	WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL2, tmp);
>   
>   	tmp = mmMMVM_L2_CNTL3_DEFAULT;
> +	if (adev->gmc.translate_further) {
> +		tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, BANK_SELECT, 12);
> +		tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3,
> +				    L2_CACHE_BIGK_FRAGMENT_SIZE, 9);
> +	} else {
> +		tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, BANK_SELECT, 9);
> +		tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3,
> +				    L2_CACHE_BIGK_FRAGMENT_SIZE, 6);
> +	}
>   	WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL3, tmp);
>   
>   	tmp = mmMMVM_L2_CNTL4_DEFAULT;