[PATCH] drm/amdgpu/arcturus: properly set BANK_SELECT and FRAGMENT_SIZE

[Christian König]

Am 30.10.19 um 18:32 schrieb Alex Deucher:
> These were not aligned for optimal performance for GPUVM.
>
> Signed-off-by: Alex Deucher <alexander.deucher at amd.com>

Reviewed-by: Christian König <christian.koenig at amd.com>

> ---
>   drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c | 9 +++++++++
>   1 file changed, 9 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c
> index 657970f9ebfb..2c5adfe803a2 100644
> --- a/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c
> +++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c
> @@ -219,6 +219,15 @@ static void mmhub_v9_4_init_cache_regs(struct amdgpu_device *adev, int hubid)
>   			    hubid * MMHUB_INSTANCE_REGISTER_OFFSET, tmp);
>   
>   	tmp = mmVML2PF0_VM_L2_CNTL3_DEFAULT;
> +	if (adev->gmc.translate_further) {
> +		tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL3, BANK_SELECT, 12);
> +		tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL3,
> +				    L2_CACHE_BIGK_FRAGMENT_SIZE, 9);
> +	} else {
> +		tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL3, BANK_SELECT, 9);
> +		tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL3,
> +				    L2_CACHE_BIGK_FRAGMENT_SIZE, 6);
> +	}
>   	WREG32_SOC15_OFFSET(MMHUB, 0, mmVML2PF0_VM_L2_CNTL3,
>   			    hubid * MMHUB_INSTANCE_REGISTER_OFFSET, tmp);
>