[PATCH] drm/amdgpu: Allow to reset to EERPOM table.

[Grodzovsky, Andrey]

What about adding new value to existing ras_ctl debugfs file ?

Andrey

________________________________________
From: Alex Deucher <alexdeucher at gmail.com>
Sent: 07 September 2019 09:42:47
To: Grodzovsky, Andrey
Cc: amd-gfx list; Zhou1, Tao; Chen, Guchun
Subject: Re: [PATCH] drm/amdgpu: Allow to reset to EERPOM table.

On Fri, Sep 6, 2019 at 11:13 AM Andrey Grodzovsky
<andrey.grodzovsky at amd.com> wrote:
>
> The table grows quickly during debug/development effort when
> multiple RAS errors are injected. Allow to avoid this by setting
> table header back to empty if needed.
>

Please make this a debugfs file rather than a module parameter so that
it an be updated at runtime and more easily handled on a per card
basis.

Alex

> Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky at amd.com>
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu.h            | 1 +
>  drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c        | 8 ++++++++
>  drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c | 3 ++-
>  3 files changed, 11 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> index 0d11aa8..405c55a 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> @@ -169,6 +169,7 @@ extern int amdgpu_discovery;
>  extern int amdgpu_mes;
>  extern int amdgpu_noretry;
>  extern int amdgpu_force_asic_type;
> +extern int amdgpu_ras_eeprom_reset;
>
>  #ifdef CONFIG_DRM_AMDGPU_SI
>  extern int amdgpu_si_support;
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> index 5a7f929..6e101a5 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> @@ -145,6 +145,7 @@ int amdgpu_discovery = -1;
>  int amdgpu_mes = 0;
>  int amdgpu_noretry = 1;
>  int amdgpu_force_asic_type = -1;
> +int amdgpu_ras_eeprom_reset = -1;
>
>  struct amdgpu_mgpu_info mgpu_info = {
>         .mutex = __MUTEX_INITIALIZER(mgpu_info.mutex),
> @@ -530,6 +531,13 @@ MODULE_PARM_DESC(ras_mask, "Mask of RAS features to enable (default 0xffffffff),
>  module_param_named(ras_mask, amdgpu_ras_mask, uint, 0444);
>
>  /**
> + * DOC: ras_eeprom_reset (int)
> + * Reset EEPROM table to zerro entries.
> + */
> +MODULE_PARM_DESC(ras_eeprom_reset, "Reset RAS EEPROM table to zerro entries (1 = reset, -1 = auto (default - don't reset)");
> +module_param_named(ras_eeprom_reset, amdgpu_ras_eeprom_reset, int, 0444);
> +
> +/**
>   * DOC: si_support (int)
>   * Set SI support driver. This parameter works after set config CONFIG_DRM_AMDGPU_SI. For SI asic, when radeon driver is enabled,
>   * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available,
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c
> index 43dd4ab..75c6fc0 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c
> @@ -140,7 +140,8 @@ int amdgpu_ras_eeprom_init(struct amdgpu_ras_eeprom_control *control)
>
>         __decode_table_header_from_buff(hdr, &buff[2]);
>
> -       if (hdr->header == EEPROM_TABLE_HDR_VAL) {
> +       if (amdgpu_ras_eeprom_reset != 1 &&
> +           hdr->header == EEPROM_TABLE_HDR_VAL) {
>                 control->num_recs = (hdr->tbl_size - EEPROM_TABLE_HEADER_SIZE) /
>                                     EEPROM_TABLE_RECORD_SIZE;
>                 DRM_DEBUG_DRIVER("Found existing EEPROM table with %d records",
> --
> 2.7.4
>
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