[PATCH 1/3] drm/amdgpu: move umc late init from gmc to umc block
Christian König
ckoenig.leichtzumerken at gmail.com
Tue Sep 10 08:13:07 UTC 2019
Am 10.09.19 um 08:31 schrieb Zhou1, Tao:
> umc late init is umc specific, it's more suitable to be put in umc block
>
> Signed-off-by: Tao Zhou <tao.zhou1 at amd.com>
Maybe rename amdgpu_ras.h into amdgpu_umc.h then, but apart from that
Acked-by: Christian König <christian.koenig at amd.com> for this patch.
> ---
> drivers/gpu/drm/amd/amdgpu/Makefile | 2 +-
> drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c | 48 ----------------
> drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h | 2 -
> drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c | 73 +++++++++++++++++++++++++
> drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h | 2 +
> drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 8 ++-
> drivers/gpu/drm/amd/amdgpu/umc_v6_1.c | 1 +
> 7 files changed, 82 insertions(+), 54 deletions(-)
> create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile b/drivers/gpu/drm/amd/amdgpu/Makefile
> index 84614a71bb4d..91369c823ce2 100644
> --- a/drivers/gpu/drm/amd/amdgpu/Makefile
> +++ b/drivers/gpu/drm/amd/amdgpu/Makefile
> @@ -55,7 +55,7 @@ amdgpu-y += amdgpu_device.o amdgpu_kms.o \
> amdgpu_vf_error.o amdgpu_sched.o amdgpu_debugfs.o amdgpu_ids.o \
> amdgpu_gmc.o amdgpu_mmhub.o amdgpu_xgmi.o amdgpu_csa.o amdgpu_ras.o amdgpu_vm_cpu.o \
> amdgpu_vm_sdma.o amdgpu_pmu.o amdgpu_discovery.o amdgpu_ras_eeprom.o amdgpu_nbio.o \
> - smu_v11_0_i2c.o
> + amdgpu_umc.o smu_v11_0_i2c.o
>
> amdgpu-$(CONFIG_PERF_EVENTS) += amdgpu_pmu.o
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
> index 51890b1d8522..dc044eec188e 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
> @@ -304,51 +304,3 @@ bool amdgpu_gmc_filter_faults(struct amdgpu_device *adev, uint64_t addr,
> gmc->fault_hash[hash].idx = gmc->last_fault++;
> return false;
> }
> -
> -int amdgpu_gmc_ras_late_init(struct amdgpu_device *adev,
> - void *ras_ih_info)
> -{
> - int r;
> - struct ras_ih_if *ih_info = (struct ras_ih_if *)ras_ih_info;
> - struct ras_fs_if fs_info = {
> - .sysfs_name = "umc_err_count",
> - .debugfs_name = "umc_err_inject",
> - };
> -
> - if (!ih_info)
> - return -EINVAL;
> -
> - if (!adev->gmc.umc_ras_if) {
> - adev->gmc.umc_ras_if = kmalloc(sizeof(struct ras_common_if), GFP_KERNEL);
> - if (!adev->gmc.umc_ras_if)
> - return -ENOMEM;
> - adev->gmc.umc_ras_if->block = AMDGPU_RAS_BLOCK__UMC;
> - adev->gmc.umc_ras_if->type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE;
> - adev->gmc.umc_ras_if->sub_block_index = 0;
> - strcpy(adev->gmc.umc_ras_if->name, "umc");
> - }
> - ih_info->head = fs_info.head = *adev->gmc.umc_ras_if;
> -
> - r = amdgpu_ras_late_init(adev, adev->gmc.umc_ras_if,
> - &fs_info, ih_info);
> - if (r)
> - goto free;
> -
> - if (amdgpu_ras_is_supported(adev, adev->gmc.umc_ras_if->block)) {
> - r = amdgpu_irq_get(adev, &adev->gmc.ecc_irq, 0);
> - if (r)
> - goto late_fini;
> - } else {
> - r = 0;
> - goto free;
> - }
> -
> - return 0;
> -
> -late_fini:
> - amdgpu_ras_late_fini(adev, adev->gmc.umc_ras_if, ih_info);
> -free:
> - kfree(adev->gmc.umc_ras_if);
> - adev->gmc.umc_ras_if = NULL;
> - return r;
> -}
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
> index 232a8ff5642b..d3be51ba6349 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
> @@ -234,7 +234,5 @@ void amdgpu_gmc_agp_location(struct amdgpu_device *adev,
> struct amdgpu_gmc *mc);
> bool amdgpu_gmc_filter_faults(struct amdgpu_device *adev, uint64_t addr,
> uint16_t pasid, uint64_t timestamp);
> -int amdgpu_gmc_ras_late_init(struct amdgpu_device *adev,
> - void *ih_info);
>
> #endif
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c
> new file mode 100644
> index 000000000000..c8de127097ab
> --- /dev/null
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c
> @@ -0,0 +1,73 @@
> +/*
> + * Copyright 2019 Advanced Micro Devices, Inc.
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice shall be included in
> + * all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
> + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
> + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> + * OTHER DEALINGS IN THE SOFTWARE.
> + *
> + */
> +
> +#include "amdgpu.h"
> +#include "amdgpu_ras.h"
> +
> +int amdgpu_umc_ras_late_init(struct amdgpu_device *adev, void *ras_ih_info)
> +{
> + int r;
> + struct ras_ih_if *ih_info = (struct ras_ih_if *)ras_ih_info;
> + struct ras_fs_if fs_info = {
> + .sysfs_name = "umc_err_count",
> + .debugfs_name = "umc_err_inject",
> + };
> +
> + if (!ih_info)
> + return -EINVAL;
> +
> + if (!adev->gmc.umc_ras_if) {
> + adev->gmc.umc_ras_if =
> + kmalloc(sizeof(struct ras_common_if), GFP_KERNEL);
> + if (!adev->gmc.umc_ras_if)
> + return -ENOMEM;
> + adev->gmc.umc_ras_if->block = AMDGPU_RAS_BLOCK__UMC;
> + adev->gmc.umc_ras_if->type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE;
> + adev->gmc.umc_ras_if->sub_block_index = 0;
> + strcpy(adev->gmc.umc_ras_if->name, "umc");
> + }
> + ih_info->head = fs_info.head = *adev->gmc.umc_ras_if;
> +
> + r = amdgpu_ras_late_init(adev, adev->gmc.umc_ras_if,
> + &fs_info, ih_info);
> + if (r)
> + goto free;
> +
> + if (amdgpu_ras_is_supported(adev, adev->gmc.umc_ras_if->block)) {
> + r = amdgpu_irq_get(adev, &adev->gmc.ecc_irq, 0);
> + if (r)
> + goto late_fini;
> + } else {
> + r = 0;
> + goto free;
> + }
> +
> + return 0;
> +
> +late_fini:
> + amdgpu_ras_late_fini(adev, adev->gmc.umc_ras_if, ih_info);
> +free:
> + kfree(adev->gmc.umc_ras_if);
> + adev->gmc.umc_ras_if = NULL;
> + return r;
> +}
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h
> index 975afa04df09..6f22c9704555 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h
> @@ -55,6 +55,7 @@
>
> struct amdgpu_umc_funcs {
> void (*ras_init)(struct amdgpu_device *adev);
> + int (*ras_late_init)(struct amdgpu_device *adev, void *ras_ih_info);
> void (*query_ras_error_count)(struct amdgpu_device *adev,
> void *ras_error_status);
> void (*query_ras_error_address)(struct amdgpu_device *adev,
> @@ -79,4 +80,5 @@ struct amdgpu_umc {
> const struct amdgpu_umc_funcs *funcs;
> };
>
> +int amdgpu_umc_ras_late_init(struct amdgpu_device *adev, void *ras_ih_info);
> #endif
> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> index 0d06c7901d26..7ec01b22a8fe 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> @@ -793,9 +793,11 @@ static int gmc_v9_0_ecc_late_init(void *handle)
> .cb = gmc_v9_0_process_ras_data_cb,
> };
>
> - r = amdgpu_gmc_ras_late_init(adev, &umc_ih_info);
> - if (r)
> - return r;
> + if (adev->umc.funcs && adev->umc.funcs->ras_late_init) {
> + r = adev->umc.funcs->ras_late_init(adev, &umc_ih_info);
> + if (r)
> + return r;
> + }
>
> if (adev->mmhub_funcs && adev->mmhub_funcs->ras_late_init) {
> r = adev->mmhub_funcs->ras_late_init(adev);
> diff --git a/drivers/gpu/drm/amd/amdgpu/umc_v6_1.c b/drivers/gpu/drm/amd/amdgpu/umc_v6_1.c
> index 09e316a22f1a..4cdb5c04cd17 100644
> --- a/drivers/gpu/drm/amd/amdgpu/umc_v6_1.c
> +++ b/drivers/gpu/drm/amd/amdgpu/umc_v6_1.c
> @@ -273,6 +273,7 @@ static void umc_v6_1_ras_init(struct amdgpu_device *adev)
>
> const struct amdgpu_umc_funcs umc_v6_1_funcs = {
> .ras_init = umc_v6_1_ras_init,
> + .ras_late_init = amdgpu_umc_ras_late_init,
> .query_ras_error_count = umc_v6_1_query_ras_error_count,
> .query_ras_error_address = umc_v6_1_query_ras_error_address,
> .enable_umc_index_mode = umc_v6_1_enable_umc_index_mode,
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