[PATCH] drm/amdgpu: remove gfx9 NGG
Christian König
ckoenig.leichtzumerken at gmail.com
Fri Sep 20 14:27:30 UTC 2019
Am 20.09.19 um 04:15 schrieb Marek Olšák:
> From: Marek Olšák <marek.olsak at amd.com>
>
> Never used.
>
> Signed-off-by: Marek Olšák <marek.olsak at amd.com>
Acked-by: Christian König <christian.koenig at amd.com>
Nice cleanup,
Christian.
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu.h | 5 -
> drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 41 -----
> drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h | 25 ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 11 --
> drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 195 ------------------------
> 5 files changed, 277 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> index 6ff02bb60140..80116e63e209 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> @@ -140,25 +140,20 @@ extern int amdgpu_dc;
> extern int amdgpu_sched_jobs;
> extern int amdgpu_sched_hw_submission;
> extern uint amdgpu_pcie_gen_cap;
> extern uint amdgpu_pcie_lane_cap;
> extern uint amdgpu_cg_mask;
> extern uint amdgpu_pg_mask;
> extern uint amdgpu_sdma_phase_quantum;
> extern char *amdgpu_disable_cu;
> extern char *amdgpu_virtual_display;
> extern uint amdgpu_pp_feature_mask;
> -extern int amdgpu_ngg;
> -extern int amdgpu_prim_buf_per_se;
> -extern int amdgpu_pos_buf_per_se;
> -extern int amdgpu_cntl_sb_buf_per_se;
> -extern int amdgpu_param_buf_per_se;
> extern int amdgpu_job_hang_limit;
> extern int amdgpu_lbpw;
> extern int amdgpu_compute_multipipe;
> extern int amdgpu_gpu_recovery;
> extern int amdgpu_emu_mode;
> extern uint amdgpu_smu_memory_pool_size;
> extern uint amdgpu_dc_feature_mask;
> extern uint amdgpu_dm_abm_level;
> extern struct amdgpu_mgpu_info mgpu_info;
> extern int amdgpu_ras_enable;
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> index b49ed39c1fea..cbe4ef4813f8 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> @@ -119,25 +119,20 @@ int amdgpu_sched_jobs = 32;
> int amdgpu_sched_hw_submission = 2;
> uint amdgpu_pcie_gen_cap = 0;
> uint amdgpu_pcie_lane_cap = 0;
> uint amdgpu_cg_mask = 0xffffffff;
> uint amdgpu_pg_mask = 0xffffffff;
> uint amdgpu_sdma_phase_quantum = 32;
> char *amdgpu_disable_cu = NULL;
> char *amdgpu_virtual_display = NULL;
> /* OverDrive(bit 14) disabled by default*/
> uint amdgpu_pp_feature_mask = 0xffffbfff;
> -int amdgpu_ngg = 0;
> -int amdgpu_prim_buf_per_se = 0;
> -int amdgpu_pos_buf_per_se = 0;
> -int amdgpu_cntl_sb_buf_per_se = 0;
> -int amdgpu_param_buf_per_se = 0;
> int amdgpu_job_hang_limit = 0;
> int amdgpu_lbpw = -1;
> int amdgpu_compute_multipipe = -1;
> int amdgpu_gpu_recovery = -1; /* auto */
> int amdgpu_emu_mode = 0;
> uint amdgpu_smu_memory_pool_size = 0;
> /* FBC (bit 0) disabled by default*/
> uint amdgpu_dc_feature_mask = 0;
> int amdgpu_async_gfx_ring = 1;
> int amdgpu_mcbp = 0;
> @@ -443,56 +438,20 @@ module_param_named(disable_cu, amdgpu_disable_cu, charp, 0444);
> * DOC: virtual_display (charp)
> * Set to enable virtual display feature. This feature provides a virtual display hardware on headless boards
> * or in virtualized environments. It will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x. It's the pci address of
> * the device, plus the number of crtcs to expose. E.g., 0000:26:00.0,4 would enable 4 virtual crtcs on the pci
> * device at 26:00.0. The default is NULL.
> */
> MODULE_PARM_DESC(virtual_display,
> "Enable virtual display feature (the virtual_display will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x)");
> module_param_named(virtual_display, amdgpu_virtual_display, charp, 0444);
>
> -/**
> - * DOC: ngg (int)
> - * Set to enable Next Generation Graphics (1 = enable). The default is 0 (disabled).
> - */
> -MODULE_PARM_DESC(ngg, "Next Generation Graphics (1 = enable, 0 = disable(default depending on gfx))");
> -module_param_named(ngg, amdgpu_ngg, int, 0444);
> -
> -/**
> - * DOC: prim_buf_per_se (int)
> - * Override the size of Primitive Buffer per Shader Engine in Byte. The default is 0 (depending on gfx).
> - */
> -MODULE_PARM_DESC(prim_buf_per_se, "the size of Primitive Buffer per Shader Engine (default depending on gfx)");
> -module_param_named(prim_buf_per_se, amdgpu_prim_buf_per_se, int, 0444);
> -
> -/**
> - * DOC: pos_buf_per_se (int)
> - * Override the size of Position Buffer per Shader Engine in Byte. The default is 0 (depending on gfx).
> - */
> -MODULE_PARM_DESC(pos_buf_per_se, "the size of Position Buffer per Shader Engine (default depending on gfx)");
> -module_param_named(pos_buf_per_se, amdgpu_pos_buf_per_se, int, 0444);
> -
> -/**
> - * DOC: cntl_sb_buf_per_se (int)
> - * Override the size of Control Sideband per Shader Engine in Byte. The default is 0 (depending on gfx).
> - */
> -MODULE_PARM_DESC(cntl_sb_buf_per_se, "the size of Control Sideband per Shader Engine (default depending on gfx)");
> -module_param_named(cntl_sb_buf_per_se, amdgpu_cntl_sb_buf_per_se, int, 0444);
> -
> -/**
> - * DOC: param_buf_per_se (int)
> - * Override the size of Off-Chip Parameter Cache per Shader Engine in Byte.
> - * The default is 0 (depending on gfx).
> - */
> -MODULE_PARM_DESC(param_buf_per_se, "the size of Off-Chip Parameter Cache per Shader Engine (default depending on gfx)");
> -module_param_named(param_buf_per_se, amdgpu_param_buf_per_se, int, 0444);
> -
> /**
> * DOC: job_hang_limit (int)
> * Set how much time allow a job hang and not drop it. The default is 0.
> */
> MODULE_PARM_DESC(job_hang_limit, "how much time allow a job hang and not drop it (default 0)");
> module_param_named(job_hang_limit, amdgpu_job_hang_limit, int ,0444);
>
> /**
> * DOC: lbpw (int)
> * Override Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable). The default is -1 (auto, enabled).
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
> index 6ed0560d7299..59c5464c96be 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
> @@ -193,42 +193,20 @@ struct amdgpu_gfx_funcs {
> uint32_t size, uint32_t *dst);
> void (*read_wave_sgprs)(struct amdgpu_device *adev, uint32_t simd,
> uint32_t wave, uint32_t start, uint32_t size,
> uint32_t *dst);
> void (*select_me_pipe_q)(struct amdgpu_device *adev, u32 me, u32 pipe,
> u32 queue, u32 vmid);
> int (*ras_error_inject)(struct amdgpu_device *adev, void *inject_if);
> int (*query_ras_error_count) (struct amdgpu_device *adev, void *ras_error_status);
> };
>
> -struct amdgpu_ngg_buf {
> - struct amdgpu_bo *bo;
> - uint64_t gpu_addr;
> - uint32_t size;
> - uint32_t bo_size;
> -};
> -
> -enum {
> - NGG_PRIM = 0,
> - NGG_POS,
> - NGG_CNTL,
> - NGG_PARAM,
> - NGG_BUF_MAX
> -};
> -
> -struct amdgpu_ngg {
> - struct amdgpu_ngg_buf buf[NGG_BUF_MAX];
> - uint32_t gds_reserve_addr;
> - uint32_t gds_reserve_size;
> - bool init;
> -};
> -
> struct sq_work {
> struct work_struct work;
> unsigned ih_data;
> };
>
> struct amdgpu_pfp {
> struct amdgpu_bo *pfp_fw_obj;
> uint64_t pfp_fw_gpu_addr;
> uint32_t *pfp_fw_ptr;
> };
> @@ -303,23 +281,20 @@ struct amdgpu_gfx {
> uint32_t gfx_current_status;
> /* ce ram size*/
> unsigned ce_ram_size;
> struct amdgpu_cu_info cu_info;
> const struct amdgpu_gfx_funcs *funcs;
>
> /* reset mask */
> uint32_t grbm_soft_reset;
> uint32_t srbm_soft_reset;
>
> - /* NGG */
> - struct amdgpu_ngg ngg;
> -
> /* gfx off */
> bool gfx_off_state; /* true: enabled, false: disabled */
> struct mutex gfx_off_mutex;
> uint32_t gfx_off_req_count; /* default 1, enable gfx off: dec 1, disable gfx off: add 1 */
> struct delayed_work gfx_off_delay_work;
>
> /* pipe reservation */
> struct mutex pipe_reserve_mutex;
> DECLARE_BITMAP (pipe_reserve_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
> index 7c68974fe8f2..6cc79d3a4e26 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
> @@ -760,31 +760,20 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file
> dev_info.ce_ram_size = adev->gfx.ce_ram_size;
> memcpy(&dev_info.cu_ao_bitmap[0], &adev->gfx.cu_info.ao_cu_bitmap[0],
> sizeof(adev->gfx.cu_info.ao_cu_bitmap));
> memcpy(&dev_info.cu_bitmap[0], &adev->gfx.cu_info.bitmap[0],
> sizeof(adev->gfx.cu_info.bitmap));
> dev_info.vram_type = adev->gmc.vram_type;
> dev_info.vram_bit_width = adev->gmc.vram_width;
> dev_info.vce_harvest_config = adev->vce.harvest_config;
> dev_info.gc_double_offchip_lds_buf =
> adev->gfx.config.double_offchip_lds_buf;
> -
> - if (amdgpu_ngg) {
> - dev_info.prim_buf_gpu_addr = adev->gfx.ngg.buf[NGG_PRIM].gpu_addr;
> - dev_info.prim_buf_size = adev->gfx.ngg.buf[NGG_PRIM].size;
> - dev_info.pos_buf_gpu_addr = adev->gfx.ngg.buf[NGG_POS].gpu_addr;
> - dev_info.pos_buf_size = adev->gfx.ngg.buf[NGG_POS].size;
> - dev_info.cntl_sb_buf_gpu_addr = adev->gfx.ngg.buf[NGG_CNTL].gpu_addr;
> - dev_info.cntl_sb_buf_size = adev->gfx.ngg.buf[NGG_CNTL].size;
> - dev_info.param_buf_gpu_addr = adev->gfx.ngg.buf[NGG_PARAM].gpu_addr;
> - dev_info.param_buf_size = adev->gfx.ngg.buf[NGG_PARAM].size;
> - }
> dev_info.wave_front_size = adev->gfx.cu_info.wave_front_size;
> dev_info.num_shader_visible_vgprs = adev->gfx.config.max_gprs;
> dev_info.num_cu_per_sh = adev->gfx.config.max_cu_per_sh;
> dev_info.num_tcc_blocks = adev->gfx.config.max_texture_channel_caches;
> dev_info.gs_vgt_table_depth = adev->gfx.config.gs_vgt_table_depth;
> dev_info.gs_prim_buffer_depth = adev->gfx.config.gs_prim_buffer_depth;
> dev_info.max_gs_waves_per_vgt = adev->gfx.config.max_gs_threads;
>
> if (adev->family >= AMDGPU_FAMILY_NV)
> dev_info.pa_sc_tile_steering_override =
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> index 9a1f91cf0ee8..266ef874f2a3 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> @@ -1946,204 +1946,20 @@ static int gfx_v9_0_gpu_early_init(struct amdgpu_device *adev)
> NUM_SHADER_ENGINES);
> adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 +
> REG_GET_FIELD(
> adev->gfx.config.gb_addr_config,
> GB_ADDR_CONFIG,
> PIPE_INTERLEAVE_SIZE));
>
> return 0;
> }
>
> -static int gfx_v9_0_ngg_create_buf(struct amdgpu_device *adev,
> - struct amdgpu_ngg_buf *ngg_buf,
> - int size_se,
> - int default_size_se)
> -{
> - int r;
> -
> - if (size_se < 0) {
> - dev_err(adev->dev, "Buffer size is invalid: %d\n", size_se);
> - return -EINVAL;
> - }
> - size_se = size_se ? size_se : default_size_se;
> -
> - ngg_buf->size = size_se * adev->gfx.config.max_shader_engines;
> - r = amdgpu_bo_create_kernel(adev, ngg_buf->size,
> - PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
> - &ngg_buf->bo,
> - &ngg_buf->gpu_addr,
> - NULL);
> - if (r) {
> - dev_err(adev->dev, "(%d) failed to create NGG buffer\n", r);
> - return r;
> - }
> - ngg_buf->bo_size = amdgpu_bo_size(ngg_buf->bo);
> -
> - return r;
> -}
> -
> -static int gfx_v9_0_ngg_fini(struct amdgpu_device *adev)
> -{
> - int i;
> -
> - for (i = 0; i < NGG_BUF_MAX; i++)
> - amdgpu_bo_free_kernel(&adev->gfx.ngg.buf[i].bo,
> - &adev->gfx.ngg.buf[i].gpu_addr,
> - NULL);
> -
> - memset(&adev->gfx.ngg.buf[0], 0,
> - sizeof(struct amdgpu_ngg_buf) * NGG_BUF_MAX);
> -
> - adev->gfx.ngg.init = false;
> -
> - return 0;
> -}
> -
> -static int gfx_v9_0_ngg_init(struct amdgpu_device *adev)
> -{
> - int r;
> -
> - if (!amdgpu_ngg || adev->gfx.ngg.init == true)
> - return 0;
> -
> - /* GDS reserve memory: 64 bytes alignment */
> - adev->gfx.ngg.gds_reserve_size = ALIGN(5 * 4, 0x40);
> - adev->gds.gds_size -= adev->gfx.ngg.gds_reserve_size;
> - adev->gfx.ngg.gds_reserve_addr = RREG32_SOC15(GC, 0, mmGDS_VMID0_BASE);
> - adev->gfx.ngg.gds_reserve_addr += RREG32_SOC15(GC, 0, mmGDS_VMID0_SIZE);
> -
> - /* Primitive Buffer */
> - r = gfx_v9_0_ngg_create_buf(adev, &adev->gfx.ngg.buf[NGG_PRIM],
> - amdgpu_prim_buf_per_se,
> - 64 * 1024);
> - if (r) {
> - dev_err(adev->dev, "Failed to create Primitive Buffer\n");
> - goto err;
> - }
> -
> - /* Position Buffer */
> - r = gfx_v9_0_ngg_create_buf(adev, &adev->gfx.ngg.buf[NGG_POS],
> - amdgpu_pos_buf_per_se,
> - 256 * 1024);
> - if (r) {
> - dev_err(adev->dev, "Failed to create Position Buffer\n");
> - goto err;
> - }
> -
> - /* Control Sideband */
> - r = gfx_v9_0_ngg_create_buf(adev, &adev->gfx.ngg.buf[NGG_CNTL],
> - amdgpu_cntl_sb_buf_per_se,
> - 256);
> - if (r) {
> - dev_err(adev->dev, "Failed to create Control Sideband Buffer\n");
> - goto err;
> - }
> -
> - /* Parameter Cache, not created by default */
> - if (amdgpu_param_buf_per_se <= 0)
> - goto out;
> -
> - r = gfx_v9_0_ngg_create_buf(adev, &adev->gfx.ngg.buf[NGG_PARAM],
> - amdgpu_param_buf_per_se,
> - 512 * 1024);
> - if (r) {
> - dev_err(adev->dev, "Failed to create Parameter Cache\n");
> - goto err;
> - }
> -
> -out:
> - adev->gfx.ngg.init = true;
> - return 0;
> -err:
> - gfx_v9_0_ngg_fini(adev);
> - return r;
> -}
> -
> -static int gfx_v9_0_ngg_en(struct amdgpu_device *adev)
> -{
> - struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0];
> - int r;
> - u32 data, base;
> -
> - if (!amdgpu_ngg)
> - return 0;
> -
> - /* Program buffer size */
> - data = REG_SET_FIELD(0, WD_BUF_RESOURCE_1, INDEX_BUF_SIZE,
> - adev->gfx.ngg.buf[NGG_PRIM].size >> 8);
> - data = REG_SET_FIELD(data, WD_BUF_RESOURCE_1, POS_BUF_SIZE,
> - adev->gfx.ngg.buf[NGG_POS].size >> 8);
> - WREG32_SOC15(GC, 0, mmWD_BUF_RESOURCE_1, data);
> -
> - data = REG_SET_FIELD(0, WD_BUF_RESOURCE_2, CNTL_SB_BUF_SIZE,
> - adev->gfx.ngg.buf[NGG_CNTL].size >> 8);
> - data = REG_SET_FIELD(data, WD_BUF_RESOURCE_2, PARAM_BUF_SIZE,
> - adev->gfx.ngg.buf[NGG_PARAM].size >> 10);
> - WREG32_SOC15(GC, 0, mmWD_BUF_RESOURCE_2, data);
> -
> - /* Program buffer base address */
> - base = lower_32_bits(adev->gfx.ngg.buf[NGG_PRIM].gpu_addr);
> - data = REG_SET_FIELD(0, WD_INDEX_BUF_BASE, BASE, base);
> - WREG32_SOC15(GC, 0, mmWD_INDEX_BUF_BASE, data);
> -
> - base = upper_32_bits(adev->gfx.ngg.buf[NGG_PRIM].gpu_addr);
> - data = REG_SET_FIELD(0, WD_INDEX_BUF_BASE_HI, BASE_HI, base);
> - WREG32_SOC15(GC, 0, mmWD_INDEX_BUF_BASE_HI, data);
> -
> - base = lower_32_bits(adev->gfx.ngg.buf[NGG_POS].gpu_addr);
> - data = REG_SET_FIELD(0, WD_POS_BUF_BASE, BASE, base);
> - WREG32_SOC15(GC, 0, mmWD_POS_BUF_BASE, data);
> -
> - base = upper_32_bits(adev->gfx.ngg.buf[NGG_POS].gpu_addr);
> - data = REG_SET_FIELD(0, WD_POS_BUF_BASE_HI, BASE_HI, base);
> - WREG32_SOC15(GC, 0, mmWD_POS_BUF_BASE_HI, data);
> -
> - base = lower_32_bits(adev->gfx.ngg.buf[NGG_CNTL].gpu_addr);
> - data = REG_SET_FIELD(0, WD_CNTL_SB_BUF_BASE, BASE, base);
> - WREG32_SOC15(GC, 0, mmWD_CNTL_SB_BUF_BASE, data);
> -
> - base = upper_32_bits(adev->gfx.ngg.buf[NGG_CNTL].gpu_addr);
> - data = REG_SET_FIELD(0, WD_CNTL_SB_BUF_BASE_HI, BASE_HI, base);
> - WREG32_SOC15(GC, 0, mmWD_CNTL_SB_BUF_BASE_HI, data);
> -
> - /* Clear GDS reserved memory */
> - r = amdgpu_ring_alloc(ring, 17);
> - if (r) {
> - DRM_ERROR("amdgpu: NGG failed to lock ring %s (%d).\n",
> - ring->name, r);
> - return r;
> - }
> -
> - gfx_v9_0_write_data_to_reg(ring, 0, false,
> - SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE),
> - (adev->gds.gds_size +
> - adev->gfx.ngg.gds_reserve_size));
> -
> - amdgpu_ring_write(ring, PACKET3(PACKET3_DMA_DATA, 5));
> - amdgpu_ring_write(ring, (PACKET3_DMA_DATA_CP_SYNC |
> - PACKET3_DMA_DATA_DST_SEL(1) |
> - PACKET3_DMA_DATA_SRC_SEL(2)));
> - amdgpu_ring_write(ring, 0);
> - amdgpu_ring_write(ring, 0);
> - amdgpu_ring_write(ring, adev->gfx.ngg.gds_reserve_addr);
> - amdgpu_ring_write(ring, 0);
> - amdgpu_ring_write(ring, PACKET3_DMA_DATA_CMD_RAW_WAIT |
> - adev->gfx.ngg.gds_reserve_size);
> -
> - gfx_v9_0_write_data_to_reg(ring, 0, false,
> - SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE), 0);
> -
> - amdgpu_ring_commit(ring);
> -
> - return 0;
> -}
> -
> static int gfx_v9_0_compute_ring_init(struct amdgpu_device *adev, int ring_id,
> int mec, int pipe, int queue)
> {
> int r;
> unsigned irq_type;
> struct amdgpu_ring *ring = &adev->gfx.compute_ring[ring_id];
>
> ring = &adev->gfx.compute_ring[ring_id];
>
> /* mec0 is me1 */
> @@ -2297,24 +2113,20 @@ static int gfx_v9_0_sw_init(void *handle)
> r = amdgpu_gfx_mqd_sw_init(adev, sizeof(struct v9_mqd_allocation));
> if (r)
> return r;
>
> adev->gfx.ce_ram_size = 0x8000;
>
> r = gfx_v9_0_gpu_early_init(adev);
> if (r)
> return r;
>
> - r = gfx_v9_0_ngg_init(adev);
> - if (r)
> - return r;
> -
> return 0;
> }
>
>
> static int gfx_v9_0_sw_fini(void *handle)
> {
> int i;
> struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>
> if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX) &&
> @@ -2334,21 +2146,20 @@ static int gfx_v9_0_sw_fini(void *handle)
> for (i = 0; i < adev->gfx.num_gfx_rings; i++)
> amdgpu_ring_fini(&adev->gfx.gfx_ring[i]);
> for (i = 0; i < adev->gfx.num_compute_rings; i++)
> amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
>
> amdgpu_gfx_mqd_sw_fini(adev);
> amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq.ring, &adev->gfx.kiq.irq);
> amdgpu_gfx_kiq_fini(adev);
>
> gfx_v9_0_mec_fini(adev);
> - gfx_v9_0_ngg_fini(adev);
> amdgpu_bo_unref(&adev->gfx.rlc.clear_state_obj);
> if (adev->asic_type == CHIP_RAVEN || adev->asic_type == CHIP_RENOIR) {
> amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj,
> &adev->gfx.rlc.cp_table_gpu_addr,
> (void **)&adev->gfx.rlc.cp_table_ptr);
> }
> gfx_v9_0_free_microcode(adev);
>
> return 0;
> }
> @@ -3864,26 +3675,20 @@ static int gfx_v9_0_hw_init(void *handle)
> return r;
>
> r = adev->gfx.rlc.funcs->resume(adev);
> if (r)
> return r;
>
> r = gfx_v9_0_cp_resume(adev);
> if (r)
> return r;
>
> - if (adev->asic_type != CHIP_ARCTURUS) {
> - r = gfx_v9_0_ngg_en(adev);
> - if (r)
> - return r;
> - }
> -
> return r;
> }
>
> static int gfx_v9_0_kcq_disable(struct amdgpu_device *adev)
> {
> int r, i;
> struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring;
>
> r = amdgpu_ring_alloc(kiq_ring, 6 * adev->gfx.num_compute_rings);
> if (r)
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