[PATCH 1/2] drm/amd/powerplay: Add mode2 mode for GPU RESET

[Gong, Curry]

Hi Aaron:

Help to review again.

-----Original Message-----
From: Liu, Aaron <Aaron.Liu at amd.com> 
Sent: Monday, September 23, 2019 2:41 PM
To: Gong, Curry <Curry.Gong at amd.com>; amd-gfx at lists.freedesktop.org
Cc: Gong, Curry <Curry.Gong at amd.com>
Subject: RE: [PATCH 1/2] drm/amd/powerplay: Add mode2 mode for GPU RESET

Hi curry,

1. You can separate the patch into 2 patches, one is workaround in smu_suspend and another is the implementation of mode2_reset.
2. hwmgr.h is used for amdgpu_powerplay instead of amdgpu_smu. You can define it directly in amdgpu_smu.h

BR,
Aaron Liu

> -----Original Message-----
> From: amd-gfx <amd-gfx-bounces at lists.freedesktop.org> On Behalf Of 
> chen gong
> Sent: Monday, September 23, 2019 2:14 PM
> To: amd-gfx at lists.freedesktop.org
> Cc: Gong, Curry <Curry.Gong at amd.com>
> Subject: [PATCH 1/2] drm/amd/powerplay: Add mode2 mode for GPU RESET
> 
> Changes to function "smu_suspend" in amdgpu_smu.c is a workaround.
> 
> We should get real information about if baco is enabled or not, while 
> we always consider APU SMU feature as enabled in current code.
> 
> I know APU do not support baco mode for GPU reset, so I use "adev->flags"
> to skip function "smu_feature_is_enabled".
> 
> Signed-off-by: chen gong <curry.gong at amd.com>
> ---
>  drivers/gpu/drm/amd/powerplay/amdgpu_smu.c     | 5 ++++-
>  drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 3 +++
>  drivers/gpu/drm/amd/powerplay/smu_v12_0.c      | 6 ++++++
>  3 files changed, 13 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> index 90fa444..e51d727 100644
> --- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> +++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> @@ -1363,7 +1363,10 @@ static int smu_suspend(void *handle)
>  	int ret;
>  	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>  	struct smu_context *smu = &adev->smu;
> -	bool baco_feature_is_enabled = smu_feature_is_enabled(smu,
> SMU_FEATURE_BACO_BIT);
> +	bool baco_feature_is_enabled = false;
> +
> +	if (!(adev->flags & AMD_IS_APU))
> +		baco_feature_is_enabled = smu_feature_is_enabled(smu, 
> +SMU_FEATURE_BACO_BIT);
> 
>  	ret = smu_system_features_control(smu, false);
>  	if (ret)
> diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
> b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
> index 45da21d..35e8b0c 100644
> --- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
> +++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
> @@ -537,6 +537,7 @@ struct smu_funcs
>  	enum smu_baco_state (*baco_get_state)(struct smu_context *smu);
>  	int (*baco_set_state)(struct smu_context *smu, enum smu_baco_state 
> state);
>  	int (*baco_reset)(struct smu_context *smu);
> +    int (*mode2_reset)(struct smu_context *smu);
>  	int (*get_dpm_ultimate_freq)(struct smu_context *smu, enum 
> smu_clk_type clk_type, uint32_t *min, uint32_t *max);  };
> 
> @@ -760,6 +761,8 @@ struct smu_funcs
>  	((smu)->funcs->baco_get_state? (smu)->funcs-
> >baco_get_state((smu), (state)) : 0)  #define smu_baco_reset(smu) \
>  	((smu)->funcs->baco_reset? (smu)->funcs->baco_reset((smu)) : 0)
> +#define smu_mode2_reset(smu) \
> +    ((smu)->funcs->mode2_reset? (smu)->funcs->mode2_reset((smu)) : 0)
>  #define smu_asic_set_performance_level(smu, level) \
>  	((smu)->ppt_funcs->set_performance_level? (smu)->ppt_funcs-
> >set_performance_level((smu), (level)) : -EINVAL);  #define
> smu_dump_pptable(smu) \ diff --git
> a/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
> b/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
> index 24274c9..f762a98 100644
> --- a/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
> +++ b/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
> @@ -30,6 +30,7 @@
>  #include "soc15_common.h"
>  #include "atom.h"
>  #include "renoir_ppt.h"
> +#include "hwmgr.h"
> 
>  #include "asic_reg/mp/mp_12_0_0_offset.h"
>  #include "asic_reg/mp/mp_12_0_0_sh_mask.h"
> @@ -380,6 +381,10 @@ static int
> smu_v12_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk
>  	return ret;
>  }
> 
> +static int smu_v12_0_mode2_reset(struct smu_context *smu){
> +	return smu_v12_0_send_msg_with_param(smu,
> +SMU_MSG_GfxDeviceDriverReset, SMU_ASIC_RESET_MODE_2); }
> +
>  static const struct smu_funcs smu_v12_0_funcs = {
>  	.check_fw_status = smu_v12_0_check_fw_status,
>  	.check_fw_version = smu_v12_0_check_fw_version, @@ -394,6
> +399,7 @@ static const struct smu_funcs smu_v12_0_funcs = {
>  	.fini_smc_tables = smu_v12_0_fini_smc_tables,
>  	.populate_smc_tables = smu_v12_0_populate_smc_tables,
>  	.get_dpm_ultimate_freq = smu_v12_0_get_dpm_ultimate_freq,
> +	.mode2_reset = smu_v12_0_mode2_reset,
>  };
> 
>  void smu_v12_0_set_smu_funcs(struct smu_context *smu)
> --
> 2.7.4
> 
> _______________________________________________
> amd-gfx mailing list
> amd-gfx at lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
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