[PATCH] drm/amdgpu: fix an UMC hw arbitrator bug(v2)
Alex Deucher
alexdeucher at gmail.com
Tue Sep 24 12:40:58 UTC 2019
On Tue, Sep 24, 2019 at 4:09 AM Monk Liu <Monk.Liu at amd.com> wrote:
>
> issue:
> the UMC6 h/w bug is that when MCLK is doing the switch
> in the middle of a page access being preempted by high
> priority client (e.g. DISPLAY) then UMC and the mclk switch
> would stuck there due to deadlock
>
> how:
> fixed by disabling auto PreChg for UMC to avoid high
> priority client preempting other client's access on
> the same page, thus the deadlock could be avoided
>
> Signed-off-by: Monk Liu <Monk.Liu at amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/Makefile | 2 +-
> drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h | 1 +
> drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 7 +++++++
> drivers/gpu/drm/amd/amdgpu/umc_v6_0.c | 37 +++++++++++++++++++++++++++++++++
> drivers/gpu/drm/amd/amdgpu/umc_v6_0.h | 31 +++++++++++++++++++++++++++
> 5 files changed, 77 insertions(+), 1 deletion(-)
> create mode 100644 drivers/gpu/drm/amd/amdgpu/umc_v6_0.c
> create mode 100644 drivers/gpu/drm/amd/amdgpu/umc_v6_0.h
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile b/drivers/gpu/drm/amd/amdgpu/Makefile
> index c3cd271..508e93c 100644
> --- a/drivers/gpu/drm/amd/amdgpu/Makefile
> +++ b/drivers/gpu/drm/amd/amdgpu/Makefile
> @@ -84,7 +84,7 @@ amdgpu-y += \
>
> # add UMC block
> amdgpu-y += \
> - umc_v6_1.o
> + umc_v6_1.o umc_v6_0.o
>
> # add IH block
> amdgpu-y += \
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h
> index 3ec36d9..17d3ec1 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h
> @@ -63,6 +63,7 @@ struct amdgpu_umc_funcs {
> void (*enable_umc_index_mode)(struct amdgpu_device *adev,
> uint32_t umc_instance);
> void (*disable_umc_index_mode)(struct amdgpu_device *adev);
> + void (*patch_for_umc)(struct amdgpu_device *adev);
Maybe something like init_registers as the callback name to better
match other IP callbacks like nbio. With that fixed:
Reviewed-by: Alex Deucher <alexander.deucher at amd.com>
> };
>
> struct amdgpu_umc {
> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> index 6102dea..7047d8f 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> @@ -51,6 +51,7 @@
> #include "gfxhub_v1_1.h"
> #include "mmhub_v9_4.h"
> #include "umc_v6_1.h"
> +#include "umc_v6_0.h"
>
> #include "ivsrcid/vmc/irqsrcs_vmc_1_0.h"
>
> @@ -696,6 +697,9 @@ static void gmc_v9_0_set_gmc_funcs(struct amdgpu_device *adev)
> static void gmc_v9_0_set_umc_funcs(struct amdgpu_device *adev)
> {
> switch (adev->asic_type) {
> + case CHIP_VEGA10:
> + adev->umc.funcs = &umc_v6_0_funcs;
> + break;
> case CHIP_VEGA20:
> adev->umc.max_ras_err_cnt_per_query = UMC_V6_1_TOTAL_CHANNEL_NUM;
> adev->umc.channel_inst_num = UMC_V6_1_CHANNEL_INSTANCE_NUM;
> @@ -1302,6 +1306,9 @@ static int gmc_v9_0_gart_enable(struct amdgpu_device *adev)
> for (i = 0; i < adev->num_vmhubs; ++i)
> gmc_v9_0_flush_gpu_tlb(adev, 0, i, 0);
>
> + if (adev->umc.funcs && adev->umc.funcs->patch_for_umc)
> + adev->umc.funcs->patch_for_umc(adev);
> +
> DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
> (unsigned)(adev->gmc.gart_size >> 20),
> (unsigned long long)amdgpu_bo_gpu_offset(adev->gart.bo));
> diff --git a/drivers/gpu/drm/amd/amdgpu/umc_v6_0.c b/drivers/gpu/drm/amd/amdgpu/umc_v6_0.c
> new file mode 100644
> index 0000000..ab04420
> --- /dev/null
> +++ b/drivers/gpu/drm/amd/amdgpu/umc_v6_0.c
> @@ -0,0 +1,37 @@
> +/*
> + * Copyright 2019 Advanced Micro Devices, Inc.
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice shall be included in
> + * all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
> + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
> + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> + * OTHER DEALINGS IN THE SOFTWARE.
> + *
> + */
> +#include "umc_v6_0.h"
> +#include "amdgpu.h"
> +
> +static void umc_v6_0_patch(struct amdgpu_device *adev)
> +{
> + unsigned i,j;
> +
> + for (i = 0; i < 4; i++)
> + for (j = 0; j < 4; j++)
> + WREG32((i*0x100000 + 0x5010c + j*0x2000)/4, 0x1002);
> +}
> +
> +const struct amdgpu_umc_funcs umc_v6_0_funcs = {
> + .patch_for_umc = umc_v6_0_patch,
> +};
> diff --git a/drivers/gpu/drm/amd/amdgpu/umc_v6_0.h b/drivers/gpu/drm/amd/amdgpu/umc_v6_0.h
> new file mode 100644
> index 0000000..109f1a5
> --- /dev/null
> +++ b/drivers/gpu/drm/amd/amdgpu/umc_v6_0.h
> @@ -0,0 +1,31 @@
> +/*
> + * Copyright 2019 Advanced Micro Devices, Inc.
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice shall be included in
> + * all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
> + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
> + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> + * OTHER DEALINGS IN THE SOFTWARE.
> + *
> + */
> +#ifndef __UMC_V6_0_H__
> +#define __UMC_V6_0_H__
> +
> +#include "soc15_common.h"
> +#include "amdgpu.h"
> +
> +extern const struct amdgpu_umc_funcs umc_v6_0_funcs;
> +
> +#endif
> --
> 2.7.4
>
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