[PATCH] drm/amdgpu: Add SMUIO values for other I2C controller v2
Russell, Kent
Kent.Russell at amd.com
Wed Sep 25 21:21:50 UTC 2019
That's the fun part 😉 Working on adding checks for which chip is requested for shared functionality, or separate functions for separated functionality.
Kent
-----Original Message-----
From: Grodzovsky, Andrey <Andrey.Grodzovsky at amd.com>
Sent: Wednesday, September 25, 2019 2:11 PM
To: Russell, Kent <Kent.Russell at amd.com>; amd-gfx at lists.freedesktop.org
Subject: Re: [PATCH] drm/amdgpu: Add SMUIO values for other I2C controller v2
Reviewed-by: Andrey Grodzovsky <andrey.grodzovsky at amd.com>
How are you planning to use them given the hard coded use of CSKVII2C (instance zero I2C engine) in I2C controller code ?
Andrey
On 9/25/19 5:03 PM, Russell, Kent wrote:
> These are the offsets for CKSVII2C1, and match up with the values
> already added for CKSVII2C
>
> v2: Don't remove some of the CSKVII2C values
>
> Change-Id: I5ed88bb31253ccaf4ed4ae6f4959040c0da2f6d0
> Signed-off-by: Kent Russell <kent.russell at amd.com>
> ---
> .../asic_reg/smuio/smuio_11_0_0_offset.h | 92 +++++++++
> .../asic_reg/smuio/smuio_11_0_0_sh_mask.h | 176 ++++++++++++++++++
> 2 files changed, 268 insertions(+)
>
> diff --git
> a/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_11_0_0_offset.h
> b/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_11_0_0_offset.h
> index d3876052562b..687d6843c258 100644
> --- a/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_11_0_0_offset.h
> +++ b/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_11_0_0_offset.h
> @@ -121,6 +121,98 @@
> #define mmCKSVII2C_IC_COMP_VERSION_BASE_IDX 0
> #define mmCKSVII2C_IC_COMP_TYPE 0x006d
> #define mmCKSVII2C_IC_COMP_TYPE_BASE_IDX 0
> +#define mmCKSVII2C1_IC_CON 0x0080
> +#define mmCKSVII2C1_IC_CON_BASE_IDX 0
> +#define mmCKSVII2C1_IC_TAR 0x0081
> +#define mmCKSVII2C1_IC_TAR_BASE_IDX 0
> +#define mmCKSVII2C1_IC_SAR 0x0082
> +#define mmCKSVII2C1_IC_SAR_BASE_IDX 0
> +#define mmCKSVII2C1_IC_HS_MADDR 0x0083
> +#define mmCKSVII2C1_IC_HS_MADDR_BASE_IDX 0
> +#define mmCKSVII2C1_IC_DATA_CMD 0x0084
> +#define mmCKSVII2C1_IC_DATA_CMD_BASE_IDX 0
> +#define mmCKSVII2C1_IC_SS_SCL_HCNT 0x0085
> +#define mmCKSVII2C1_IC_SS_SCL_HCNT_BASE_IDX 0
> +#define mmCKSVII2C1_IC_SS_SCL_LCNT 0x0086
> +#define mmCKSVII2C1_IC_SS_SCL_LCNT_BASE_IDX 0
> +#define mmCKSVII2C1_IC_FS_SCL_HCNT 0x0087
> +#define mmCKSVII2C1_IC_FS_SCL_HCNT_BASE_IDX 0
> +#define mmCKSVII2C1_IC_FS_SCL_LCNT 0x0088
> +#define mmCKSVII2C1_IC_FS_SCL_LCNT_BASE_IDX 0
> +#define mmCKSVII2C1_IC_HS_SCL_HCNT 0x0089
> +#define mmCKSVII2C1_IC_HS_SCL_HCNT_BASE_IDX 0
> +#define mmCKSVII2C1_IC_HS_SCL_LCNT 0x008a
> +#define mmCKSVII2C1_IC_HS_SCL_LCNT_BASE_IDX 0
> +#define mmCKSVII2C1_IC_INTR_STAT 0x008b
> +#define mmCKSVII2C1_IC_INTR_STAT_BASE_IDX 0
> +#define mmCKSVII2C1_IC_INTR_MASK 0x008c
> +#define mmCKSVII2C1_IC_INTR_MASK_BASE_IDX 0
> +#define mmCKSVII2C1_IC_RAW_INTR_STAT 0x008d
> +#define mmCKSVII2C1_IC_RAW_INTR_STAT_BASE_IDX 0
> +#define mmCKSVII2C1_IC_RX_TL 0x008e
> +#define mmCKSVII2C1_IC_RX_TL_BASE_IDX 0
> +#define mmCKSVII2C1_IC_TX_TL 0x008f
> +#define mmCKSVII2C1_IC_TX_TL_BASE_IDX 0
> +#define mmCKSVII2C1_IC_CLR_INTR 0x0090
> +#define mmCKSVII2C1_IC_CLR_INTR_BASE_IDX 0
> +#define mmCKSVII2C1_IC_CLR_RX_UNDER 0x0091
> +#define mmCKSVII2C1_IC_CLR_RX_UNDER_BASE_IDX 0
> +#define mmCKSVII2C1_IC_CLR_RX_OVER 0x0092
> +#define mmCKSVII2C1_IC_CLR_RX_OVER_BASE_IDX 0
> +#define mmCKSVII2C1_IC_CLR_TX_OVER 0x0093
> +#define mmCKSVII2C1_IC_CLR_TX_OVER_BASE_IDX 0
> +#define mmCKSVII2C1_IC_CLR_RD_REQ 0x0094
> +#define mmCKSVII2C1_IC_CLR_RD_REQ_BASE_IDX 0
> +#define mmCKSVII2C1_IC_CLR_TX_ABRT 0x0095
> +#define mmCKSVII2C1_IC_CLR_TX_ABRT_BASE_IDX 0
> +#define mmCKSVII2C1_IC_CLR_RX_DONE 0x0096
> +#define mmCKSVII2C1_IC_CLR_RX_DONE_BASE_IDX 0
> +#define mmCKSVII2C1_IC_CLR_ACTIVITY 0x0097
> +#define mmCKSVII2C1_IC_CLR_ACTIVITY_BASE_IDX 0
> +#define mmCKSVII2C1_IC_CLR_STOP_DET 0x0098
> +#define mmCKSVII2C1_IC_CLR_STOP_DET_BASE_IDX 0
> +#define mmCKSVII2C1_IC_CLR_START_DET 0x0099
> +#define mmCKSVII2C1_IC_CLR_START_DET_BASE_IDX 0
> +#define mmCKSVII2C1_IC_CLR_GEN_CALL 0x009a
> +#define mmCKSVII2C1_IC_CLR_GEN_CALL_BASE_IDX 0
> +#define mmCKSVII2C1_IC_ENABLE 0x009b
> +#define mmCKSVII2C1_IC_ENABLE_BASE_IDX 0
> +#define mmCKSVII2C1_IC_STATUS 0x009c
> +#define mmCKSVII2C1_IC_STATUS_BASE_IDX 0
> +#define mmCKSVII2C1_IC_TXFLR 0x009d
> +#define mmCKSVII2C1_IC_TXFLR_BASE_IDX 0
> +#define mmCKSVII2C1_IC_RXFLR 0x009e
> +#define mmCKSVII2C1_IC_RXFLR_BASE_IDX 0
> +#define mmCKSVII2C1_IC_SDA_HOLD 0x009f
> +#define mmCKSVII2C1_IC_SDA_HOLD_BASE_IDX 0
> +#define mmCKSVII2C1_IC_TX_ABRT_SOURCE 0x00a0
> +#define mmCKSVII2C1_IC_TX_ABRT_SOURCE_BASE_IDX 0
> +#define mmCKSVII2C1_IC_SLV_DATA_NACK_ONLY 0x00a1
> +#define mmCKSVII2C1_IC_SLV_DATA_NACK_ONLY_BASE_IDX 0
> +#define mmCKSVII2C1_IC_DMA_CR 0x00a2
> +#define mmCKSVII2C1_IC_DMA_CR_BASE_IDX 0
> +#define mmCKSVII2C1_IC_DMA_TDLR 0x00a3
> +#define mmCKSVII2C1_IC_DMA_TDLR_BASE_IDX 0
> +#define mmCKSVII2C1_IC_DMA_RDLR 0x00a4
> +#define mmCKSVII2C1_IC_DMA_RDLR_BASE_IDX 0
> +#define mmCKSVII2C1_IC_SDA_SETUP 0x00a5
> +#define mmCKSVII2C1_IC_SDA_SETUP_BASE_IDX 0
> +#define mmCKSVII2C1_IC_ACK_GENERAL_CALL 0x00a6
> +#define mmCKSVII2C1_IC_ACK_GENERAL_CALL_BASE_IDX 0
> +#define mmCKSVII2C1_IC_ENABLE_STATUS 0x00a7
> +#define mmCKSVII2C1_IC_ENABLE_STATUS_BASE_IDX 0
> +#define mmCKSVII2C1_IC_FS_SPKLEN 0x00a8
> +#define mmCKSVII2C1_IC_FS_SPKLEN_BASE_IDX 0
> +#define mmCKSVII2C1_IC_HS_SPKLEN 0x00a9
> +#define mmCKSVII2C1_IC_HS_SPKLEN_BASE_IDX 0
> +#define mmCKSVII2C1_IC_CLR_RESTART_DET 0x00aa
> +#define mmCKSVII2C1_IC_CLR_RESTART_DET_BASE_IDX 0
> +#define mmCKSVII2C1_IC_COMP_PARAM_1 0x00ab
> +#define mmCKSVII2C1_IC_COMP_PARAM_1_BASE_IDX 0
> +#define mmCKSVII2C1_IC_COMP_VERSION 0x00ac
> +#define mmCKSVII2C1_IC_COMP_VERSION_BASE_IDX 0
> +#define mmCKSVII2C1_IC_COMP_TYPE 0x00ad
> +#define mmCKSVII2C1_IC_COMP_TYPE_BASE_IDX 0
> #define mmSMUIO_MP_RESET_INTR 0x00c1
> #define mmSMUIO_MP_RESET_INTR_BASE_IDX 0
> #define mmSMUIO_SOC_HALT 0x00c2
> diff --git
> a/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_11_0_0_sh_mask.h
> b/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_11_0_0_sh_mask.h
> index f8afa3518bf2..6905a9618127 100644
> ---
> a/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_11_0_0_sh_mask.h
> +++ b/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_11_0_0_sh_mask.
> +++ h
> @@ -268,6 +268,182 @@
> //CKSVII2C_IC_COMP_TYPE
> #define CKSVII2C_IC_COMP_TYPE__COMP_TYPE__SHIFT 0x0
> #define CKSVII2C_IC_COMP_TYPE__COMP_TYPE_MASK 0xFFFFFFFFL
> +//CKSVII2C1_IC_CON
> +#define CKSVII2C1_IC_CON__IC1_MASTER_MODE__SHIFT 0x0
> +#define CKSVII2C1_IC_CON__IC1_MAX_SPEED_MODE__SHIFT 0x1
> +#define CKSVII2C1_IC_CON__IC1_10BITADDR_SLAVE__SHIFT 0x3
> +#define CKSVII2C1_IC_CON__IC1_10BITADDR_MASTER__SHIFT 0x4
> +#define CKSVII2C1_IC_CON__IC1_RESTART_EN__SHIFT 0x5
> +#define CKSVII2C1_IC_CON__IC1_SLAVE_DISABLE__SHIFT 0x6
> +#define CKSVII2C1_IC_CON__STOP1_DET_IFADDRESSED__SHIFT 0x7
> +#define CKSVII2C1_IC_CON__TX1_EMPTY_CTRL__SHIFT 0x8
> +#define CKSVII2C1_IC_CON__RX1_FIFO_FULL_HLD_CTRL__SHIFT 0x9
> +#define CKSVII2C1_IC_CON__IC1_MASTER_MODE_MASK 0x00000001L
> +#define CKSVII2C1_IC_CON__IC1_MAX_SPEED_MODE_MASK 0x00000006L
> +#define CKSVII2C1_IC_CON__IC1_10BITADDR_SLAVE_MASK 0x00000008L
> +#define CKSVII2C1_IC_CON__IC1_10BITADDR_MASTER_MASK 0x00000010L
> +#define CKSVII2C1_IC_CON__IC1_RESTART_EN_MASK 0x00000020L
> +#define CKSVII2C1_IC_CON__IC1_SLAVE_DISABLE_MASK 0x00000040L
> +#define CKSVII2C1_IC_CON__STOP1_DET_IFADDRESSED_MASK 0x00000080L
> +#define CKSVII2C1_IC_CON__TX1_EMPTY_CTRL_MASK 0x00000100L
> +#define CKSVII2C1_IC_CON__RX1_FIFO_FULL_HLD_CTRL_MASK 0x00000200L
> +//CKSVII2C1_IC_TAR
> +#define CKSVII2C1_IC_TAR__IC1_TAR__SHIFT 0x0
> +#define CKSVII2C1_IC_TAR__GC1_OR_START__SHIFT 0xa
> +#define CKSVII2C1_IC_TAR__SPECIAL1__SHIFT 0xb
> +#define CKSVII2C1_IC_TAR__IC1_10BITADDR_MASTER__SHIFT 0xc
> +#define CKSVII2C1_IC_TAR__IC1_TAR_MASK 0x000003FFL
> +#define CKSVII2C1_IC_TAR__GC1_OR_START_MASK 0x00000400L
> +#define CKSVII2C1_IC_TAR__SPECIAL1_MASK 0x00000800L
> +#define CKSVII2C1_IC_TAR__IC1_10BITADDR_MASTER_MASK 0x00001000L
> +//CKSVII2C1_IC_SAR
> +#define CKSVII2C1_IC_SAR__IC1_SAR__SHIFT 0x0
> +#define CKSVII2C1_IC_SAR__IC1_SAR_MASK 0x000003FFL
> +//CKSVII2C1_IC_HS_MADDR
> +#define CKSVII2C1_IC_HS_MADDR__IC1_HS_MADDR__SHIFT 0x0
> +#define CKSVII2C1_IC_HS_MADDR__IC1_HS_MADDR_MASK 0x00000007L
> +//CKSVII2C1_IC_DATA_CMD
> +#define CKSVII2C1_IC_DATA_CMD__DAT1__SHIFT 0x0
> +#define CKSVII2C1_IC_DATA_CMD__CMD1__SHIFT 0x8
> +#define CKSVII2C1_IC_DATA_CMD__STOP1__SHIFT 0x9
> +#define CKSVII2C1_IC_DATA_CMD__RESTART1__SHIFT 0xa
> +#define CKSVII2C1_IC_DATA_CMD__DAT1_MASK 0x000000FFL
> +#define CKSVII2C1_IC_DATA_CMD__CMD1_MASK 0x00000100L
> +#define CKSVII2C1_IC_DATA_CMD__STOP1_MASK 0x00000200L
> +#define CKSVII2C1_IC_DATA_CMD__RESTART1_MASK 0x00000400L
> +//CKSVII2C1_IC_SS_SCL_HCNT
> +#define CKSVII2C1_IC_SS_SCL_HCNT__IC1_SS_SCL_HCNT__SHIFT 0x0
> +#define CKSVII2C1_IC_SS_SCL_HCNT__IC1_SS_SCL_HCNT_MASK 0x0000FFFFL
> +//CKSVII2C1_IC_SS_SCL_LCNT
> +#define CKSVII2C1_IC_SS_SCL_LCNT__IC1_SS_SCL_LCNT__SHIFT 0x0
> +#define CKSVII2C1_IC_SS_SCL_LCNT__IC1_SS_SCL_LCNT_MASK 0x0000FFFFL
> +//CKSVII2C1_IC_FS_SCL_HCNT
> +#define CKSVII2C1_IC_FS_SCL_HCNT__IC1_FS_SCL_HCNT__SHIFT 0x0
> +#define CKSVII2C1_IC_FS_SCL_HCNT__IC1_FS_SCL_HCNT_MASK 0x0000FFFFL
> +//CKSVII2C1_IC_FS_SCL_LCNT
> +#define CKSVII2C1_IC_FS_SCL_LCNT__IC1_FS_SCL_LCNT__SHIFT 0x0
> +#define CKSVII2C1_IC_FS_SCL_LCNT__IC1_FS_SCL_LCNT_MASK 0x0000FFFFL
> +//CKSVII2C1_IC_HS_SCL_HCNT
> +#define CKSVII2C1_IC_HS_SCL_HCNT__IC1_HS_SCL_HCNT__SHIFT 0x0
> +#define CKSVII2C1_IC_HS_SCL_HCNT__IC1_HS_SCL_HCNT_MASK 0x0000FFFFL
> +//CKSVII2C1_IC_HS_SCL_LCNT
> +#define CKSVII2C1_IC_HS_SCL_LCNT__IC1_HS_SCL_LCNT__SHIFT 0x0
> +#define CKSVII2C1_IC_HS_SCL_LCNT__IC1_HS_SCL_LCNT_MASK 0x0000FFFFL
> +//CKSVII2C1_IC_INTR_STAT
> +#define CKSVII2C1_IC_INTR_STAT__R1_RX_UNDER__SHIFT 0x0
> +#define CKSVII2C1_IC_INTR_STAT__R1_RX_OVER__SHIFT 0x1
> +#define CKSVII2C1_IC_INTR_STAT__R1_RX_FULL__SHIFT 0x2
> +#define CKSVII2C1_IC_INTR_STAT__R1_TX_OVER__SHIFT 0x3
> +#define CKSVII2C1_IC_INTR_STAT__R1_TX_EMPTY__SHIFT 0x4
> +#define CKSVII2C1_IC_INTR_STAT__R1_RD_REQ__SHIFT 0x5
> +#define CKSVII2C1_IC_INTR_STAT__R1_TX_ABRT__SHIFT 0x6
> +#define CKSVII2C1_IC_INTR_STAT__R1_RX_DONE__SHIFT 0x7
> +#define CKSVII2C1_IC_INTR_STAT__R1_ACTIVITY__SHIFT 0x8
> +#define CKSVII2C1_IC_INTR_STAT__R1_STOP_DET__SHIFT 0x9
> +#define CKSVII2C1_IC_INTR_STAT__R1_START_DET__SHIFT 0xa
> +#define CKSVII2C1_IC_INTR_STAT__R1_GEN_CALL__SHIFT 0xb
> +#define CKSVII2C1_IC_INTR_STAT__R1_RESTART_DET__SHIFT 0xc
> +#define CKSVII2C1_IC_INTR_STAT__R1_MST_ON_HOLD__SHIFT 0xd
> +#define CKSVII2C1_IC_INTR_STAT__R1_RX_UNDER_MASK 0x00000001L
> +#define CKSVII2C1_IC_INTR_STAT__R1_RX_OVER_MASK 0x00000002L
> +#define CKSVII2C1_IC_INTR_STAT__R1_RX_FULL_MASK 0x00000004L
> +#define CKSVII2C1_IC_INTR_STAT__R1_TX_OVER_MASK 0x00000008L
> +#define CKSVII2C1_IC_INTR_STAT__R1_TX_EMPTY_MASK 0x00000010L
> +#define CKSVII2C1_IC_INTR_STAT__R1_RD_REQ_MASK 0x00000020L
> +#define CKSVII2C1_IC_INTR_STAT__R1_TX_ABRT_MASK 0x00000040L
> +#define CKSVII2C1_IC_INTR_STAT__R1_RX_DONE_MASK 0x00000080L
> +#define CKSVII2C1_IC_INTR_STAT__R1_ACTIVITY_MASK 0x00000100L
> +#define CKSVII2C1_IC_INTR_STAT__R1_STOP_DET_MASK 0x00000200L
> +#define CKSVII2C1_IC_INTR_STAT__R1_START_DET_MASK 0x00000400L
> +#define CKSVII2C1_IC_INTR_STAT__R1_GEN_CALL_MASK 0x00000800L
> +#define CKSVII2C1_IC_INTR_STAT__R1_RESTART_DET_MASK 0x00001000L
> +#define CKSVII2C1_IC_INTR_STAT__R1_MST_ON_HOLD_MASK 0x00002000L
> +//CKSVII2C1_IC_INTR_MASK
> +#define CKSVII2C1_IC_INTR_MASK__M1_RX_UNDER__SHIFT 0x0
> +#define CKSVII2C1_IC_INTR_MASK__M1_RX_OVER__SHIFT 0x1
> +#define CKSVII2C1_IC_INTR_MASK__M1_RX_FULL__SHIFT 0x2
> +#define CKSVII2C1_IC_INTR_MASK__M1_TX_OVER__SHIFT 0x3
> +#define CKSVII2C1_IC_INTR_MASK__M1_TX_EMPTY__SHIFT 0x4
> +#define CKSVII2C1_IC_INTR_MASK__M1_RD_REQ__SHIFT 0x5
> +#define CKSVII2C1_IC_INTR_MASK__M1_TX_ABRT__SHIFT 0x6
> +#define CKSVII2C1_IC_INTR_MASK__M1_RX_DONE__SHIFT 0x7
> +#define CKSVII2C1_IC_INTR_MASK__M1_ACTIVITY__SHIFT 0x8
> +#define CKSVII2C1_IC_INTR_MASK__M1_STOP_DET__SHIFT 0x9
> +#define CKSVII2C1_IC_INTR_MASK__M1_START_DET__SHIFT 0xa
> +#define CKSVII2C1_IC_INTR_MASK__M1_GEN_CALL__SHIFT 0xb
> +#define CKSVII2C1_IC_INTR_MASK__M1_RESTART_DET__SHIFT 0xc
> +#define CKSVII2C1_IC_INTR_MASK__M1_MST_ON_HOLD__SHIFT 0xd
> +#define CKSVII2C1_IC_INTR_MASK__M1_RX_UNDER_MASK 0x00000001L
> +#define CKSVII2C1_IC_INTR_MASK__M1_RX_OVER_MASK 0x00000002L
> +#define CKSVII2C1_IC_INTR_MASK__M1_RX_FULL_MASK 0x00000004L
> +#define CKSVII2C1_IC_INTR_MASK__M1_TX_OVER_MASK 0x00000008L
> +#define CKSVII2C1_IC_INTR_MASK__M1_TX_EMPTY_MASK 0x00000010L
> +#define CKSVII2C1_IC_INTR_MASK__M1_RD_REQ_MASK 0x00000020L
> +#define CKSVII2C1_IC_INTR_MASK__M1_TX_ABRT_MASK 0x00000040L
> +#define CKSVII2C1_IC_INTR_MASK__M1_RX_DONE_MASK 0x00000080L
> +#define CKSVII2C1_IC_INTR_MASK__M1_ACTIVITY_MASK 0x00000100L
> +#define CKSVII2C1_IC_INTR_MASK__M1_STOP_DET_MASK 0x00000200L
> +#define CKSVII2C1_IC_INTR_MASK__M1_START_DET_MASK 0x00000400L
> +#define CKSVII2C1_IC_INTR_MASK__M1_GEN_CALL_MASK 0x00000800L
> +#define CKSVII2C1_IC_INTR_MASK__M1_RESTART_DET_MASK 0x00001000L
> +#define CKSVII2C1_IC_INTR_MASK__M1_MST_ON_HOLD_MASK 0x00002000L
> +//CKSVII2C1_IC_RAW_INTR_STAT
> +//CKSVII2C1_IC_RX_TL
> +//CKSVII2C1_IC_TX_TL
> +//CKSVII2C1_IC_CLR_INTR
> +//CKSVII2C1_IC_CLR_RX_UNDER
> +//CKSVII2C1_IC_CLR_RX_OVER
> +//CKSVII2C1_IC_CLR_TX_OVER
> +//CKSVII2C1_IC_CLR_RD_REQ
> +//CKSVII2C1_IC_CLR_TX_ABRT
> +//CKSVII2C1_IC_CLR_RX_DONE
> +//CKSVII2C1_IC_CLR_ACTIVITY
> +//CKSVII2C1_IC_CLR_STOP_DET
> +//CKSVII2C1_IC_CLR_START_DET
> +//CKSVII2C1_IC_CLR_GEN_CALL
> +//CKSVII2C1_IC_ENABLE
> +#define CKSVII2C1_IC_ENABLE__ENABLE1__SHIFT 0x0
> +#define CKSVII2C1_IC_ENABLE__ABORT1__SHIFT 0x1
> +#define CKSVII2C1_IC_ENABLE__ENABLE1_MASK 0x00000001L
> +#define CKSVII2C1_IC_ENABLE__ABORT1_MASK 0x00000002L
> +//CKSVII2C1_IC_STATUS
> +#define CKSVII2C1_IC_STATUS__ACTIVITY1__SHIFT 0x0
> +#define CKSVII2C1_IC_STATUS__TFNF1__SHIFT 0x1
> +#define CKSVII2C1_IC_STATUS__TFE1__SHIFT 0x2
> +#define CKSVII2C1_IC_STATUS__RFNE1__SHIFT 0x3
> +#define CKSVII2C1_IC_STATUS__RFF1__SHIFT 0x4
> +#define CKSVII2C1_IC_STATUS__MST1_ACTIVITY__SHIFT 0x5
> +#define CKSVII2C1_IC_STATUS__SLV1_ACTIVITY__SHIFT 0x6
> +#define CKSVII2C1_IC_STATUS__ACTIVITY1_MASK 0x00000001L
> +#define CKSVII2C1_IC_STATUS__TFNF1_MASK 0x00000002L
> +#define CKSVII2C1_IC_STATUS__TFE1_MASK 0x00000004L
> +#define CKSVII2C1_IC_STATUS__RFNE1_MASK 0x00000008L
> +#define CKSVII2C1_IC_STATUS__RFF1_MASK 0x00000010L
> +#define CKSVII2C1_IC_STATUS__MST1_ACTIVITY_MASK 0x00000020L
> +#define CKSVII2C1_IC_STATUS__SLV1_ACTIVITY_MASK 0x00000040L
> +//CKSVII2C1_IC_TXFLR
> +//CKSVII2C1_IC_RXFLR
> +//CKSVII2C1_IC_SDA_HOLD
> +#define CKSVII2C1_IC_SDA_HOLD__IC1_SDA_HOLD__SHIFT 0x0
> +#define CKSVII2C1_IC_SDA_HOLD__IC1_SDA_HOLD_MASK 0x00FFFFFFL
> +//CKSVII2C1_IC_TX_ABRT_SOURCE
> +//CKSVII2C1_IC_SLV_DATA_NACK_ONLY
> +//CKSVII2C1_IC_DMA_CR
> +//CKSVII2C1_IC_DMA_TDLR
> +//CKSVII2C1_IC_DMA_RDLR
> +//CKSVII2C1_IC_SDA_SETUP
> +#define CKSVII2C1_IC_SDA_SETUP__SDA1_SETUP__SHIFT 0x0
> +#define CKSVII2C1_IC_SDA_SETUP__SDA1_SETUP_MASK 0x000000FFL
> +//CKSVII2C1_IC_ACK_GENERAL_CALL
> +#define CKSVII2C1_IC_ACK_GENERAL_CALL__ACK1_GENERAL_CALL__SHIFT 0x0
> +#define CKSVII2C1_IC_ACK_GENERAL_CALL__ACK1_GENERAL_CALL_MASK 0x00000001L
> +//CKSVII2C1_IC_ENABLE_STATUS
> +#define CKSVII2C1_IC_ENABLE_STATUS__IC1_EN__SHIFT 0x0
> +#define CKSVII2C1_IC_ENABLE_STATUS__SLV1_RX_ABORTED__SHIFT 0x1
> +#define CKSVII2C1_IC_ENABLE_STATUS__SLV1_FIFO_FILLED_AND_FLUSHED__SHIFT 0x2
> +#define CKSVII2C1_IC_ENABLE_STATUS__IC1_EN_MASK 0x00000001L
> +#define CKSVII2C1_IC_ENABLE_STATUS__SLV1_RX_ABORTED_MASK 0x00000002L
> +#define CKSVII2C1_IC_ENABLE_STATUS__SLV1_FIFO_FILLED_AND_FLUSHED_MASK 0x00000004L
> //SMUIO_MP_RESET_INTR
> #define SMUIO_MP_RESET_INTR__SMUIO_MP_RESET_INTR__SHIFT 0x0
> #define SMUIO_MP_RESET_INTR__SMUIO_MP_RESET_INTR_MASK 0x00000001L
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