[PATCH] amdgpu/drm: remove psp access on navi10 for sriov

[Felix Kuehling]

Am 2020-04-01 um 6:00 p.m. schrieb Alex Sierra:
> Navi ASICs don't require to access through PSP to osssys registers.
> This on SR-IOV configuration.
>
> Signed-off-by: Alex Sierra <alex.sierra at amd.com>

Reviewed-by: Felix Kuehling <Felix.Kuehling at amd.com>


> ---
>  drivers/gpu/drm/amd/amdgpu/navi10_ih.c | 18 +++++++++---------
>  1 file changed, 9 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
> index 6fca5206833d..f97857ed3c7e 100644
> --- a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
> +++ b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
> @@ -49,7 +49,7 @@ static void navi10_ih_enable_interrupts(struct amdgpu_device *adev)
>  
>  	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 1);
>  	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 1);
> -	if (amdgpu_sriov_vf(adev)) {
> +	if (amdgpu_sriov_vf(adev) && adev->asic_type < CHIP_NAVI10) {
>  		if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL, ih_rb_cntl)) {
>  			DRM_ERROR("PSP program IH_RB_CNTL failed!\n");
>  			return;
> @@ -64,7 +64,7 @@ static void navi10_ih_enable_interrupts(struct amdgpu_device *adev)
>  		ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1);
>  		ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING1,
>  					   RB_ENABLE, 1);
> -		if (amdgpu_sriov_vf(adev)) {
> +		if (amdgpu_sriov_vf(adev) && adev->asic_type < CHIP_NAVI10) {
>  			if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING1,
>  						ih_rb_cntl)) {
>  				DRM_ERROR("program IH_RB_CNTL_RING1 failed!\n");
> @@ -80,7 +80,7 @@ static void navi10_ih_enable_interrupts(struct amdgpu_device *adev)
>  		ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2);
>  		ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING2,
>  					   RB_ENABLE, 1);
> -		if (amdgpu_sriov_vf(adev)) {
> +		if (amdgpu_sriov_vf(adev) && adev->asic_type < CHIP_NAVI10) {
>  			if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING2,
>  						ih_rb_cntl)) {
>  				DRM_ERROR("program IH_RB_CNTL_RING2 failed!\n");
> @@ -106,7 +106,7 @@ static void navi10_ih_disable_interrupts(struct amdgpu_device *adev)
>  
>  	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 0);
>  	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 0);
> -	if (amdgpu_sriov_vf(adev)) {
> +	if (amdgpu_sriov_vf(adev) && adev->asic_type < CHIP_NAVI10) {
>  		if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL, ih_rb_cntl)) {
>  			DRM_ERROR("PSP program IH_RB_CNTL failed!\n");
>  			return;
> @@ -125,7 +125,7 @@ static void navi10_ih_disable_interrupts(struct amdgpu_device *adev)
>  		ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1);
>  		ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING1,
>  					   RB_ENABLE, 0);
> -		if (amdgpu_sriov_vf(adev)) {
> +		if (amdgpu_sriov_vf(adev) && adev->asic_type < CHIP_NAVI10) {
>  			if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING1,
>  						ih_rb_cntl)) {
>  				DRM_ERROR("program IH_RB_CNTL_RING1 failed!\n");
> @@ -145,7 +145,7 @@ static void navi10_ih_disable_interrupts(struct amdgpu_device *adev)
>  		ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2);
>  		ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING2,
>  					   RB_ENABLE, 0);
> -		if (amdgpu_sriov_vf(adev)) {
> +		if (amdgpu_sriov_vf(adev) && adev->asic_type < CHIP_NAVI10) {
>  			if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING2,
>  						ih_rb_cntl)) {
>  				DRM_ERROR("program IH_RB_CNTL_RING2 failed!\n");
> @@ -253,7 +253,7 @@ static int navi10_ih_irq_init(struct amdgpu_device *adev)
>  	ih_rb_cntl = navi10_ih_rb_cntl(ih, ih_rb_cntl);
>  	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RPTR_REARM,
>  				   !!adev->irq.msi_enabled);
> -	if (amdgpu_sriov_vf(adev)) {
> +	if (amdgpu_sriov_vf(adev) && adev->asic_type < CHIP_NAVI10) {
>  		if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL, ih_rb_cntl)) {
>  			DRM_ERROR("PSP program IH_RB_CNTL failed!\n");
>  			return -ETIMEDOUT;
> @@ -300,7 +300,7 @@ static int navi10_ih_irq_init(struct amdgpu_device *adev)
>  					   WPTR_OVERFLOW_ENABLE, 0);
>  		ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,
>  					   RB_FULL_DRAIN_ENABLE, 1);
> -		if (amdgpu_sriov_vf(adev)) {
> +		if (amdgpu_sriov_vf(adev) && adev->asic_type < CHIP_NAVI10) {
>  			if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING1,
>  						ih_rb_cntl)) {
>  				DRM_ERROR("program IH_RB_CNTL_RING1 failed!\n");
> @@ -326,7 +326,7 @@ static int navi10_ih_irq_init(struct amdgpu_device *adev)
>  		ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2);
>  		ih_rb_cntl = navi10_ih_rb_cntl(ih, ih_rb_cntl);
>  
> -		if (amdgpu_sriov_vf(adev)) {
> +		if (amdgpu_sriov_vf(adev) && adev->asic_type < CHIP_NAVI10) {
>  			if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING2,
>  						ih_rb_cntl)) {
>  				DRM_ERROR("program IH_RB_CNTL_RING2 failed!\n");