[PATCH] drm/amdgpu: add SPM golden settings for Navi10

[Alex Deucher]

On Fri, Apr 3, 2020 at 1:30 AM Tianci Yin <tianci.yin at amd.com> wrote:
>
> From: "Tianci.Yin" <tianci.yin at amd.com>
>
> Add RLC_SPM golden settings
>
> Change-Id: I616e127171293d915cb3a05dee02f51cec8d8f6f
> Signed-off-by: Tianci.Yin <tianci.yin at amd.com>
> ---
>  drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c        |    9 +
>  .../gpu/drm/amd/amdgpu/golden_gc_spm_10_1_0.h | 1058 +++++++++++++++++
>  2 files changed, 1067 insertions(+)
>  create mode 100644 drivers/gpu/drm/amd/amdgpu/golden_gc_spm_10_1_0.h
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> index 70edbbf84338..7c96a894ad37 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> @@ -48,6 +48,7 @@
>  #include "v10_structs.h"
>  #include "gfx_v10_0.h"
>  #include "nbio_v2_3.h"
> +#include "golden_gc_spm_10_1_0.h"

Can we just include the table directly in this file instead of a
separate header?  One more comment below.

>
>  /**
>   * Navi10 has two graphic rings to share each graphic pipe.
> @@ -138,6 +139,11 @@ static const struct soc15_reg_golden golden_settings_gc_10_0_nv10[] =
>         /* Pending on emulation bring up */
>  };
>
> +static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_0_nv10[] =
> +{
> +       GOLDEN_GC_SPM_10_1_0
> +};
> +
>  static const struct soc15_reg_golden golden_settings_gc_10_1_1[] =
>  {
>         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x003c0014),
> @@ -388,6 +394,9 @@ static void gfx_v10_0_init_golden_registers(struct amdgpu_device *adev)
>                 soc15_program_register_sequence(adev,
>                                                 golden_settings_gc_10_0_nv10,
>                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_0_nv10));
> +               soc15_program_register_sequence(adev,
> +                                               golden_settings_gc_rlc_spm_10_0_nv10,
> +                                               (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_0_nv10));
>                 break;
>         case CHIP_NAVI14:
>                 soc15_program_register_sequence(adev,
> diff --git a/drivers/gpu/drm/amd/amdgpu/golden_gc_spm_10_1_0.h b/drivers/gpu/drm/amd/amdgpu/golden_gc_spm_10_1_0.h
> new file mode 100644
> index 000000000000..e65af4a6fcdd
> --- /dev/null
> +++ b/drivers/gpu/drm/amd/amdgpu/golden_gc_spm_10_1_0.h

This file is missing a license.

Alex