[PATCH 3/3] drm/amd/powerplay: perform PG ungate prior to CG ungate

[Alex Deucher]

On Thu, Apr 30, 2020 at 2:44 AM Evan Quan <evan.quan at amd.com> wrote:
>
> Since gfxoff should be disabled first before trying to access those
> GC registers.
>
> Change-Id: I5bf0fbe01fa05c89bbb392ef40e11c07edfee039
> Signed-off-by: Evan Quan <evan.quan at amd.com>

Series is:
Reviewed-by: Alex Deucher <alexander.deucher at amd.com>

> ---
>  drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 6 +++---
>  drivers/gpu/drm/amd/powerplay/amdgpu_smu.c    | 6 +++---
>  2 files changed, 6 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> index fdff3e1c5e95..96c91bb70df5 100644
> --- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> +++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> @@ -322,12 +322,12 @@ static void pp_dpm_en_umd_pstate(struct pp_hwmgr  *hwmgr,
>                 if (*level & profile_mode_mask) {
>                         hwmgr->saved_dpm_level = hwmgr->dpm_level;
>                         hwmgr->en_umd_pstate = true;
> -                       amdgpu_device_ip_set_clockgating_state(hwmgr->adev,
> -                                               AMD_IP_BLOCK_TYPE_GFX,
> -                                               AMD_CG_STATE_UNGATE);
>                         amdgpu_device_ip_set_powergating_state(hwmgr->adev,
>                                         AMD_IP_BLOCK_TYPE_GFX,
>                                         AMD_PG_STATE_UNGATE);
> +                       amdgpu_device_ip_set_clockgating_state(hwmgr->adev,
> +                                               AMD_IP_BLOCK_TYPE_GFX,
> +                                               AMD_CG_STATE_UNGATE);
>                 }
>         } else {
>                 /* exit umd pstate, restore level, enable gfx cg*/
> diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> index 12810fd81d5d..e6252bcaa641 100644
> --- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> +++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> @@ -1780,12 +1780,12 @@ static int smu_enable_umd_pstate(void *handle,
>                 if (*level & profile_mode_mask) {
>                         smu_dpm_ctx->saved_dpm_level = smu_dpm_ctx->dpm_level;
>                         smu_dpm_ctx->enable_umd_pstate = true;
> -                       amdgpu_device_ip_set_clockgating_state(smu->adev,
> -                                                              AMD_IP_BLOCK_TYPE_GFX,
> -                                                              AMD_CG_STATE_UNGATE);
>                         amdgpu_device_ip_set_powergating_state(smu->adev,
>                                                                AMD_IP_BLOCK_TYPE_GFX,
>                                                                AMD_PG_STATE_UNGATE);
> +                       amdgpu_device_ip_set_clockgating_state(smu->adev,
> +                                                              AMD_IP_BLOCK_TYPE_GFX,
> +                                                              AMD_CG_STATE_UNGATE);
>                 }
>         } else {
>                 /* exit umd pstate, restore level, enable gfx cg*/
> --
> 2.26.2
>
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