[PATCH 3/8] drm/amd/display: Honor the offset for plane 0.

[daniel at ffwll.ch]

On Tue, Aug 04, 2020 at 11:31:14PM +0200, Bas Nieuwenhuizen wrote:
> With modifiers I'd like to support non-dedicated buffers for
> images.
> 
> Signed-off-by: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>

Uh, I think it'd be really good to preceed this with a bugfix (cc: stable)
which checks that the offset is 0). And then this patch here removing that
again. Or cc: stable this patch here, since we seem to have a gap in
validating addfb.
-Daniel

> ---
>  drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 14 +++++++++-----
>  1 file changed, 9 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> index 005331c772b7..abc70fbe176d 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> @@ -3623,6 +3623,7 @@ fill_plane_dcc_attributes(struct amdgpu_device *adev,
>  	struct dc *dc = adev->dm.dc;
>  	struct dc_dcc_surface_param input;
>  	struct dc_surface_dcc_cap output;
> +	uint64_t plane_address = afb->address + afb->base.offsets[0];
>  	uint32_t offset = AMDGPU_TILING_GET(info, DCC_OFFSET_256B);
>  	uint32_t i64b = AMDGPU_TILING_GET(info, DCC_INDEPENDENT_64B) != 0;
>  	uint64_t dcc_address;
> @@ -3666,7 +3667,7 @@ fill_plane_dcc_attributes(struct amdgpu_device *adev,
>  		AMDGPU_TILING_GET(info, DCC_PITCH_MAX) + 1;
>  	dcc->independent_64b_blks = i64b;
>  
> -	dcc_address = get_dcc_address(afb->address, info);
> +	dcc_address = get_dcc_address(plane_address, info);
>  	address->grph.meta_addr.low_part = lower_32_bits(dcc_address);
>  	address->grph.meta_addr.high_part = upper_32_bits(dcc_address);
>  
> @@ -3697,6 +3698,8 @@ fill_plane_buffer_attributes(struct amdgpu_device *adev,
>  	address->tmz_surface = tmz_surface;
>  
>  	if (format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) {
> +		uint64_t addr = afb->address + fb->offsets[0];
> +
>  		plane_size->surface_size.x = 0;
>  		plane_size->surface_size.y = 0;
>  		plane_size->surface_size.width = fb->width;
> @@ -3705,9 +3708,10 @@ fill_plane_buffer_attributes(struct amdgpu_device *adev,
>  			fb->pitches[0] / fb->format->cpp[0];
>  
>  		address->type = PLN_ADDR_TYPE_GRAPHICS;
> -		address->grph.addr.low_part = lower_32_bits(afb->address);
> -		address->grph.addr.high_part = upper_32_bits(afb->address);
> +		address->grph.addr.low_part = lower_32_bits(addr);
> +		address->grph.addr.high_part = upper_32_bits(addr);
>  	} else if (format < SURFACE_PIXEL_FORMAT_INVALID) {
> +		uint64_t luma_addr = afb->address + fb->offsets[0];
>  		uint64_t chroma_addr = afb->address + fb->offsets[1];
>  
>  		plane_size->surface_size.x = 0;
> @@ -3728,9 +3732,9 @@ fill_plane_buffer_attributes(struct amdgpu_device *adev,
>  
>  		address->type = PLN_ADDR_TYPE_VIDEO_PROGRESSIVE;
>  		address->video_progressive.luma_addr.low_part =
> -			lower_32_bits(afb->address);
> +			lower_32_bits(luma_addr);
>  		address->video_progressive.luma_addr.high_part =
> -			upper_32_bits(afb->address);
> +			upper_32_bits(luma_addr);
>  		address->video_progressive.chroma_addr.low_part =
>  			lower_32_bits(chroma_addr);
>  		address->video_progressive.chroma_addr.high_part =
> -- 
> 2.28.0
> 

-- 
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch