[PATCH] gpu/drm: Remove TTM_PL_FLAG_WC of VRAM to fix writecombine issue for Loongson64

[Christian König]

Am 10.08.20 um 12:50 schrieb Michel Dänzer:
> On 2020-08-09 2:13 p.m., Christian König wrote:
>> Am 08.08.20 um 15:50 schrieb Jiaxun Yang:
>>> 在 2020/8/8 下午9:41, Thomas Bogendoerfer 写道:
>>>> On Sat, Aug 08, 2020 at 03:25:02PM +0800, Tiezhu Yang wrote:
>>>>> Loongson processors have a writecombine issue that maybe failed to
>>>>> write back framebuffer used with ATI Radeon or AMD GPU at times,
>>>>> after commit 8a08e50cee66 ("drm: Permit video-buffers writecombine
>>>>> mapping for MIPS"), there exists some errors such as blurred screen
>>>>> and lockup, and so on.
>>>>>
>>>>> Remove the flag TTM_PL_FLAG_WC of VRAM to fix writecombine issue for
>>>>> Loongson64 to work well with ATI Radeon or AMD GPU, and it has no any
>>>>> influence on the other platforms.
>>>> well it's not my call to take or reject this patch, but I already
>>>> indicated it might be better to disable writecombine on the CPU
>>>> detection side (or do you have other devices where writecombining
>>>> works ?). Something like below will disbale it for all loongson64 CPUs.
>>>> If you now find out where it works and where it doesn't, you can even
>>>> reduce it to the required minium of affected CPUs.
>>> Hi Tiezhu, Thomas,
>>>
>>> Yes, writecombine works well on LS7A's internal GPU....
>>> And even works well with some AMD GPUs (in my case, RX550).
>> In this case the patch is a clear NAK since you haven't root caused the
>> issue and are just working around it in a very questionable manner.
> To be fair though, amdgpu & radeon are already disabling write-combining
> for system memory pages in 32-bit x86 kernels for similar reasons.

Yeah, well that is USWC for system memory. But this is about WC for the 
VRAM BAR.

When we don't understand or don't correctly implement something on the 
platform for USWC then this is annoying, but not a serious issue.

But when the hardware doesn't correctly implement WC for PCIe BARs, then 
this is a violation of the PCIe spec and a bit more serious issue for 
the whole platform.

We can work around that by disabling WC for PCIe BARs on the whole 
platform, or behind specific bridges or or or, but patching each 
individual driver so that they work is not really the right approach.

Cheers,
Christian.