[PATCH 1/5] drm/amd/pm: disable/enable deep sleep features on UMD pstate enter/exit

[Deucher, Alexander]

[AMD Public Use]

You can probably just squash patches 2-5 into one patch.  Either way, series is:
Reviewed-by: Alex Deucher <alexander.deucher at amd.com>


________________________________
From: Quan, Evan <Evan.Quan at amd.com>
Sent: Monday, August 17, 2020 4:29 AM
To: amd-gfx at lists.freedesktop.org <amd-gfx at lists.freedesktop.org>
Cc: Deucher, Alexander <Alexander.Deucher at amd.com>; Quan, Evan <Evan.Quan at amd.com>
Subject: [PATCH 1/5] drm/amd/pm: disable/enable deep sleep features on UMD pstate enter/exit

Add deep sleep disablement/enablement on UMD pstate entering/exiting.

Change-Id: I4fbc02bb4a390ab82293a5ff9c91f2a8beb0a3c9
Signed-off-by: Evan Quan <evan.quan at amd.com>
---
 drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h     | 1 +
 drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c   | 2 ++
 drivers/gpu/drm/amd/pm/swsmu/smu_internal.h | 1 +
 3 files changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
index 7cc707ec21c3..4c5c041af4ee 100644
--- a/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
@@ -597,6 +597,7 @@ struct pptable_funcs {
         ssize_t (*get_gpu_metrics)(struct smu_context *smu, void **table);
         int (*enable_mgpu_fan_boost)(struct smu_context *smu);
         int (*gfx_ulv_control)(struct smu_context *smu, bool enablement);
+       int (*deep_sleep_control)(struct smu_context *smu, bool enablement);
 };

 typedef enum {
diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
index 221b5c923ce1..8eb5b92903cd 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
@@ -1441,6 +1441,7 @@ static int smu_enable_umd_pstate(void *handle,
                                                                AMD_IP_BLOCK_TYPE_GFX,
                                                                AMD_CG_STATE_UNGATE);
                         smu_gfx_ulv_control(smu, false);
+                       smu_deep_sleep_control(smu, false);
                 }
         } else {
                 /* exit umd pstate, restore level, enable gfx cg*/
@@ -1448,6 +1449,7 @@ static int smu_enable_umd_pstate(void *handle,
                         if (*level == AMD_DPM_FORCED_LEVEL_PROFILE_EXIT)
                                 *level = smu_dpm_ctx->saved_dpm_level;
                         smu_dpm_ctx->enable_umd_pstate = false;
+                       smu_deep_sleep_control(smu, true);
                         smu_gfx_ulv_control(smu, true);
                         amdgpu_device_ip_set_clockgating_state(smu->adev,
                                                                AMD_IP_BLOCK_TYPE_GFX,
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu_internal.h b/drivers/gpu/drm/amd/pm/swsmu/smu_internal.h
index 2fe29c6a00ce..c88f8fab1bae 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu_internal.h
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu_internal.h
@@ -93,6 +93,7 @@
 #define smu_get_pp_feature_mask(smu, buf)                               smu_ppt_funcs(get_pp_feature_mask, 0, smu, buf)
 #define smu_set_pp_feature_mask(smu, new_mask)                          smu_ppt_funcs(set_pp_feature_mask, 0, smu, new_mask)
 #define smu_gfx_ulv_control(smu, enablement)                            smu_ppt_funcs(gfx_ulv_control, 0, smu, enablement)
+#define smu_deep_sleep_control(smu, enablement)                                smu_ppt_funcs(deep_sleep_control, 0, smu, enablement)

 #endif
 #endif
--
2.28.0

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