[PATCH] drm/amd/powerplay: Fix hardmins not being sent to SMU for RV

[Quan, Evan]

[AMD Official Use Only - Internal Distribution Only]

Reviewed-by: Evan Quan <evan.quan at amd.com>

-----Original Message-----
From: amd-gfx <amd-gfx-bounces at lists.freedesktop.org> On Behalf Of Nicholas Kazlauskas
Sent: Friday, August 21, 2020 11:32 PM
To: amd-gfx at lists.freedesktop.org
Cc: Wu, Hersen <hersenxs.wu at amd.com>; Kazlauskas, Nicholas <Nicholas.Kazlauskas at amd.com>
Subject: [PATCH] drm/amd/powerplay: Fix hardmins not being sent to SMU for RV

[Why]
DC uses these to raise the voltage as needed for higher dispclk/dppclk
and to ensure that we have enough bandwidth to drive the displays.

There's a bug preventing these from actuially sending messages since
it's checking the actual clock (which is 0) instead of the incoming
clock (which shouldn't be 0) when deciding to send the hardmin.

[How]
Check the clocks != 0 instead of the actual clocks.

Fixes: 9ed9203c3ee7 ("drm/amd/powerplay: rv dal-pplib interface refactor powerplay part")
Cc: Hersen Wu <hersenxs.wu at amd.com>
Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas at amd.com>
---
 drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c | 9 +++------
 1 file changed, 3 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c
index c9cfe90a2947..9ee8cf8267c8 100644
--- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c
+++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c
@@ -204,8 +204,7 @@ static int smu10_set_min_deep_sleep_dcefclk(struct pp_hwmgr *hwmgr, uint32_t clo
 {
 struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);

-if (smu10_data->need_min_deep_sleep_dcefclk &&
-smu10_data->deep_sleep_dcefclk != clock) {
+if (clock && smu10_data->deep_sleep_dcefclk != clock) {
 smu10_data->deep_sleep_dcefclk = clock;
 smum_send_msg_to_smc_with_parameter(hwmgr,
 PPSMC_MSG_SetMinDeepSleepDcefclk,
@@ -219,8 +218,7 @@ static int smu10_set_hard_min_dcefclk_by_freq(struct pp_hwmgr *hwmgr, uint32_t c
 {
 struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);

-if (smu10_data->dcf_actual_hard_min_freq &&
-smu10_data->dcf_actual_hard_min_freq != clock) {
+if (clock && smu10_data->dcf_actual_hard_min_freq != clock) {
 smu10_data->dcf_actual_hard_min_freq = clock;
 smum_send_msg_to_smc_with_parameter(hwmgr,
 PPSMC_MSG_SetHardMinDcefclkByFreq,
@@ -234,8 +232,7 @@ static int smu10_set_hard_min_fclk_by_freq(struct pp_hwmgr *hwmgr, uint32_t cloc
 {
 struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);

-if (smu10_data->f_actual_hard_min_freq &&
-smu10_data->f_actual_hard_min_freq != clock) {
+if (clock && smu10_data->f_actual_hard_min_freq != clock) {
 smu10_data->f_actual_hard_min_freq = clock;
 smum_send_msg_to_smc_with_parameter(hwmgr,
 PPSMC_MSG_SetHardMinFclkByFreq,
--
2.25.1

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