[PATCH] drm/amd/display: Add DPCS regs for dcn3 link encoder
Kazlauskas, Nicholas
nicholas.kazlauskas at amd.com
Mon Aug 24 15:27:25 UTC 2020
On 2020-08-24 11:11 a.m., Bhawanpreet Lakha wrote:
> dpcs reg are missing for dcn3 link encoder regs list, so add them.
>
> Also remove
> DPCSTX_DEBUG_CONFIG and RDPCSTX_DEBUG_CONFIG as they are unused and
> cause compile errors for dcn3
>
> Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha at amd.com>
Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas at amd.com>
Regards,
Nicholas Kazlauskas
> ---
> drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.h | 2 --
> drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c | 1 +
> 2 files changed, 1 insertion(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.h b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.h
> index dcbf28dd72d4..864acd695cbb 100644
> --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.h
> +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.h
> @@ -231,8 +231,6 @@
> SRI(RDPCSTX_PHY_FUSE3, RDPCSTX, id), \
> SRI(DPCSTX_TX_CLOCK_CNTL, DPCSTX, id), \
> SRI(DPCSTX_TX_CNTL, DPCSTX, id), \
> - SRI(DPCSTX_DEBUG_CONFIG, DPCSTX, id), \
> - SRI(RDPCSTX_DEBUG_CONFIG, RDPCSTX, id), \
> SR(RDPCSTX0_RDPCSTX_SCRATCH)
>
>
> diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
> index 957fc37b971e..8be4f21169d0 100644
> --- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
> +++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
> @@ -491,6 +491,7 @@ static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = {
> [id] = {\
> LE_DCN3_REG_LIST(id), \
> UNIPHY_DCN2_REG_LIST(phyid), \
> + DPCS_DCN2_REG_LIST(id), \
> SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \
> }
>
>
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