[PATCH] drm/amd/pm: enable MP0 DPM for sienna_cichlid

[Zhou1, Tao]

[AMD Public Use]

Reviewed-by: Tao Zhou <tao.zhou1 at amd.com>

> -----Original Message-----
> From: Jiansong Chen <Jiansong.Chen at amd.com>
> Sent: Thursday, August 27, 2020 2:47 PM
> To: amd-gfx at lists.freedesktop.org
> Cc: Zhou1, Tao <Tao.Zhou1 at amd.com>; Feng, Kenneth
> <Kenneth.Feng at amd.com>; Chen, Jiansong (Simon) <Jiansong.Chen at amd.com>
> Subject: [PATCH] drm/amd/pm: enable MP0 DPM for sienna_cichlid
> 
> Enable MP0 clock DPM for sienna_cichlid.
> 
> Signed-off-by: Jiansong Chen <Jiansong.Chen at amd.com>
> Change-Id: Iee6a05a634c200f9bbb895b963365bb001a451bc
> ---
>  drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c | 4 +++-
>  1 file changed, 3 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
> b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
> index b48ac591db8b..b67931fd64b4 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
> @@ -68,7 +68,8 @@
>  	FEATURE_MASK(FEATURE_DPM_LINK_BIT)       | \
>  	FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT)     | \
>  	FEATURE_MASK(FEATURE_DPM_FCLK_BIT)	 | \
> -	FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT))
> +	FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT)	 | \
> +	FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT))
> 
>  #define SMU_11_0_7_GFX_BUSY_THRESHOLD 15
> 
> @@ -230,6 +231,7 @@ sienna_cichlid_get_allowed_feature_mask(struct
> smu_context *smu,
> 
>  	*(uint64_t *)feature_mask |=
> FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT)
>  				| FEATURE_MASK(FEATURE_DPM_FCLK_BIT)
> +				| FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT)
>  				| FEATURE_MASK(FEATURE_DS_SOCCLK_BIT)
>  				| FEATURE_MASK(FEATURE_DS_DCEFCLK_BIT)
>  				| FEATURE_MASK(FEATURE_DS_FCLK_BIT)
> --
> 2.25.1