[PATCH 1/1] drm/amdgpu: disable gpu-sched load balance for uvd

[Leo Liu]

On 2020-08-31 5:53 p.m., Alex Deucher wrote:
> On Mon, Aug 31, 2020 at 5:50 PM Leo Liu <leo.liu at amd.com> wrote:
>>
>> On 2020-08-31 1:39 p.m., Alex Deucher wrote:
>>> On Mon, Aug 31, 2020 at 10:55 AM Nirmoy <nirmodas at amd.com> wrote:
>>>> Hi Alex,
>>>>
>>>> On 8/31/20 4:17 PM, Alex Deucher wrote:
>>>>> On Mon, Aug 31, 2020 at 6:41 AM Nirmoy Das <nirmoy.das at amd.com> wrote:
>>>>>> UVD dependent jobs should run on the same udv instance.
>>>>>> This patch disables gpu scheduler's load balancer for
>>>>>> a context which binds jobs from same the context to a udv
>>>>>> instance.
>>>>> typos: udv -> uvd
>>>>> With that fixed:
>>>>> Reviewed-by: Alex Deucher <alexander.deucher at amd.com>
>>>>>
>>>>> Does VCE need a similar fix?  What about UVD_ENC?
>>>> I am not sure, can you please confirm this.
>>> @Leo Liu can you confirm?
>> Vega20 have 2 UVDs and 1 VCE, so UVD_ENC(AMDGPU_HW_IP_UVD_ENC) should
>> need the same fix.
> What about other chips?  Didn't CZ and tonga have two VCE instances?
> I guess any engine with hw contexts needs this.

Vega20  2 UVDs are identical and separated, exposed separated own set of 
rings to driver, and have their own scheduler.

For CZ and Tonga, it got 2 VCE instances internally, and just expose one 
set of rings to driver. i.e the instances will receive the IB thru the 
same ring, and different IB structures will decide that one instance or 
two instances will be used.

Regards,

Leo