[PATCH 1/1] drm/amdgpu: use AMDGPU_NUM_VMID when possible
Christian König
christian.koenig at amd.com
Tue Dec 8 12:05:33 UTC 2020
Am 08.12.20 um 11:17 schrieb Nirmoy Das:
> Replace hardcoded vmid number with AMDGPU_NUM_VMID macro.
>
> Signed-off-by: Nirmoy Das <nirmoy.das at amd.com>
Acked-by: Christian König <christian.koenig at amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 2 +-
> drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 2 +-
> drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 2 +-
> drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 2 +-
> drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 2 +-
> drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c | 2 +-
> drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 2 +-
> drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 2 +-
> drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c | 2 +-
> drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c | 2 +-
> drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c | 2 +-
> drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c | 2 +-
> 12 files changed, 12 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> index 157ae3004cc2..ba1086784525 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> @@ -4844,7 +4844,7 @@ static void gfx_v10_0_init_gds_vmid(struct amdgpu_device *adev)
> * the driver can enable them for graphics. VMID0 should maintain
> * access so that HWS firmware can save/restore entries.
> */
> - for (vmid = 1; vmid < 16; vmid++) {
> + for (vmid = 1; vmid < AMDGPU_NUM_VMID; vmid++) {
> WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * vmid, 0);
> WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * vmid, 0);
> WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, vmid, 0);
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
> index f2490f915a8b..a368724c3dfc 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
> @@ -1896,7 +1896,7 @@ static void gfx_v7_0_init_gds_vmid(struct amdgpu_device *adev)
> * the driver can enable them for graphics. VMID0 should maintain
> * access so that HWS firmware can save/restore entries.
> */
> - for (vmid = 1; vmid < 16; vmid++) {
> + for (vmid = 1; vmid < AMDGPU_NUM_VMID; vmid++) {
> WREG32(amdgpu_gds_reg_offset[vmid].mem_base, 0);
> WREG32(amdgpu_gds_reg_offset[vmid].mem_size, 0);
> WREG32(amdgpu_gds_reg_offset[vmid].gws, 0);
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> index 9a905531f837..37639214cbbb 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> @@ -3749,7 +3749,7 @@ static void gfx_v8_0_init_gds_vmid(struct amdgpu_device *adev)
> * the driver can enable them for graphics. VMID0 should maintain
> * access so that HWS firmware can save/restore entries.
> */
> - for (vmid = 1; vmid < 16; vmid++) {
> + for (vmid = 1; vmid < AMDGPU_NUM_VMID; vmid++) {
> WREG32(amdgpu_gds_reg_offset[vmid].mem_base, 0);
> WREG32(amdgpu_gds_reg_offset[vmid].mem_size, 0);
> WREG32(amdgpu_gds_reg_offset[vmid].gws, 0);
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> index 60519431ed91..fc9bb94eaaf4 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> @@ -2520,7 +2520,7 @@ static void gfx_v9_0_init_gds_vmid(struct amdgpu_device *adev)
> * the driver can enable them for graphics. VMID0 should maintain
> * access so that HWS firmware can save/restore entries.
> */
> - for (vmid = 1; vmid < 16; vmid++) {
> + for (vmid = 1; vmid < AMDGPU_NUM_VMID; vmid++) {
> WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * vmid, 0);
> WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * vmid, 0);
> WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, vmid, 0);
> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
> index 5317efc942a4..11fedcf86fae 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
> @@ -432,7 +432,7 @@ static int gmc_v10_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev,
> return 0;
> }
>
> - for (vmid = 1; vmid < 16; vmid++) {
> + for (vmid = 1; vmid < AMDGPU_NUM_VMID; vmid++) {
>
> ret = gmc_v10_0_get_atc_vmid_pasid_mapping_info(adev, vmid,
> &queried_pasid);
> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
> index 95a9117e9564..998d6c8fde79 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
> @@ -530,7 +530,7 @@ static int gmc_v6_0_gart_enable(struct amdgpu_device *adev)
> * the VMs are determined by the application and setup and assigned
> * on the fly in the vm part of radeon_gart.c
> */
> - for (i = 1; i < 16; i++) {
> + for (i = 1; i < AMDGPU_NUM_VMID; i++) {
> if (i < 8)
> WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i,
> table_addr >> 12);
> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
> index d9cb887b3a91..d06e3f5e38ae 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
> @@ -677,7 +677,7 @@ static int gmc_v7_0_gart_enable(struct amdgpu_device *adev)
> /* set vm size, must be a multiple of 4 */
> WREG32(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR, 0);
> WREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR, adev->vm_manager.max_pfn - 1);
> - for (i = 1; i < 16; i++) {
> + for (i = 1; i < AMDGPU_NUM_VMID; i++) {
> if (i < 8)
> WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i,
> table_addr >> 12);
> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
> index 65d7bc108151..e8d07109c628 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
> @@ -903,7 +903,7 @@ static int gmc_v8_0_gart_enable(struct amdgpu_device *adev)
> /* set vm size, must be a multiple of 4 */
> WREG32(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR, 0);
> WREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR, adev->vm_manager.max_pfn - 1);
> - for (i = 1; i < 16; i++) {
> + for (i = 1; i < AMDGPU_NUM_VMID; i++) {
> if (i < 8)
> WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i,
> table_addr >> 12);
> diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
> index 0309d84c887d..d7b39c07de20 100644
> --- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
> @@ -344,7 +344,7 @@ static void mmhub_v1_0_gart_disable(struct amdgpu_device *adev)
> u32 i;
>
> /* Disable all tables */
> - for (i = 0; i < 16; i++)
> + for (i = 0; i < AMDGPU_NUM_VMID; i++)
> WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT0_CNTL,
> i * hub->ctx_distance, 0);
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c
> index 57d5f8ffb764..092ff2c43658 100644
> --- a/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c
> @@ -421,7 +421,7 @@ static void mmhub_v2_0_gart_disable(struct amdgpu_device *adev)
> u32 i;
>
> /* Disable all tables */
> - for (i = 0; i < 16; i++)
> + for (i = 0; i < AMDGPU_NUM_VMID; i++)
> WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT0_CNTL,
> i * hub->ctx_distance, 0);
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c
> index fa77eae6cf47..b72c8e4ca36b 100644
> --- a/drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c
> +++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c
> @@ -376,7 +376,7 @@ static void mmhub_v2_3_gart_disable(struct amdgpu_device *adev)
> u32 i;
>
> /* Disable all tables */
> - for (i = 0; i < 16; i++)
> + for (i = 0; i < AMDGPU_NUM_VMID; i++)
> WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT0_CNTL,
> i * hub->ctx_distance, 0);
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c
> index 66748bb01b52..4a31737b6bb0 100644
> --- a/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c
> +++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c
> @@ -405,7 +405,7 @@ static void mmhub_v9_4_gart_disable(struct amdgpu_device *adev)
>
> for (j = 0; j < MMHUB_NUM_INSTANCES; j++) {
> /* Disable all tables */
> - for (i = 0; i < 16; i++)
> + for (i = 0; i < AMDGPU_NUM_VMID; i++)
> WREG32_SOC15_OFFSET(MMHUB, 0,
> mmVML2VC0_VM_CONTEXT0_CNTL,
> j * MMHUB_INSTANCE_REGISTER_OFFSET +
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