[PATCH 3/5] drm/amdgpu: switch hdp callback functions for hdp v4
Lazar, Lijo
Lijo.Lazar at amd.com
Tue Dec 29 06:27:11 UTC 2020
[AMD Public Use]
>-----Original Message-----
>From: amd-gfx <amd-gfx-bounces at lists.freedesktop.org> On Behalf Of Likun
>Gao
>Sent: Monday, December 28, 2020 2:49 PM
>To: amd-gfx at lists.freedesktop.org
>Cc: Gao, Likun <Likun.Gao at amd.com>; Zhang, Hawking
><Hawking.Zhang at amd.com>
>Subject: [PATCH 3/5] drm/amdgpu: switch hdp callback functions for hdp v4
>
>[CAUTION: External Email]
>
>From: Likun Gao <Likun.Gao at amd.com>
>
>Switch to use the HDP functions which unfied on hdp structure instead of the
>scattered hdp callback functions.
>
>Signed-off-by: Likun Gao <Likun.Gao at amd.com>
>Change-Id: I75016df403eca537fa30519e2918207461ec6f28
>---
> drivers/gpu/drm/amd/amdgpu/Makefile | 2 +-
> drivers/gpu/drm/amd/amdgpu/amdgpu.h | 7 ++-
> drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 21 +------
> drivers/gpu/drm/amd/amdgpu/soc15.c | 82 +++------------------------
> 4 files changed, 15 insertions(+), 97 deletions(-)
>
>diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile
>b/drivers/gpu/drm/amd/amdgpu/Makefile
>index c6262689e14e..d741fee91a37 100644
>--- a/drivers/gpu/drm/amd/amdgpu/Makefile
>+++ b/drivers/gpu/drm/amd/amdgpu/Makefile
>@@ -71,7 +71,7 @@ amdgpu-y += \
> vi.o mxgpu_vi.o nbio_v6_1.o soc15.o emu_soc.o mxgpu_ai.o nbio_v7_0.o
>vega10_reg_init.o \
> vega20_reg_init.o nbio_v7_4.o nbio_v2_3.o nv.o navi10_reg_init.o
>navi14_reg_init.o \
> arct_reg_init.o navi12_reg_init.o mxgpu_nv.o sienna_cichlid_reg_init.o
>vangogh_reg_init.o \
>- nbio_v7_2.o dimgrey_cavefish_reg_init.o
>+ nbio_v7_2.o dimgrey_cavefish_reg_init.o hdp_v4_0.o
>
> # add DF block
> amdgpu-y += \
>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>index 92e9d1f1207b..ae4bcdd630e6 100644
>--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>@@ -89,6 +89,7 @@
> #include "amdgpu_gfx.h"
> #include "amdgpu_sdma.h"
> #include "amdgpu_nbio.h"
>+#include "amdgpu_hdp.h"
> #include "amdgpu_dm.h"
> #include "amdgpu_virt.h"
> #include "amdgpu_csa.h"
>@@ -1209,8 +1210,10 @@ int emu_soc_asic_init(struct amdgpu_device
>*adev); #define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)-
>>asic_funcs->read_bios_from_rom((adev), (b), (l)) #define
>amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs-
>>read_register((adev), (se), (sh), (offset), (v))) #define
>amdgpu_asic_get_config_memsize(adev) (adev)->asic_funcs-
>>get_config_memsize((adev))
>-#define amdgpu_asic_flush_hdp(adev, r) (adev)->asic_funcs-
>>flush_hdp((adev), (r)) -#define amdgpu_asic_invalidate_hdp(adev, r)
>(adev)->asic_funcs->invalidate_hdp((adev), (r))
>+#define amdgpu_asic_flush_hdp(adev, r) \
>+ ((adev)->asic_funcs->flush_hdp ?
>+(adev)->asic_funcs->flush_hdp((adev), (r)) : (adev)->hdp.funcs-
>>flush_hdp((adev), (r))) #define amdgpu_asic_invalidate_hdp(adev, r) \
>+ ((adev)->asic_funcs->invalidate_hdp ?
>+(adev)->asic_funcs->invalidate_hdp((adev), (r)) :
>+(adev)->hdp.funcs->invalidate_hdp((adev), (r)))
> #define amdgpu_asic_need_full_reset(adev) (adev)->asic_funcs-
>>need_full_reset((adev))
> #define amdgpu_asic_init_doorbell_index(adev) (adev)->asic_funcs-
>>init_doorbell_index((adev))
> #define amdgpu_asic_get_pcie_usage(adev, cnt0, cnt1) ((adev)->asic_funcs-
>>get_pcie_usage((adev), (cnt0), (cnt1))) diff --git
>a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
>b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
>index e22268f9dba7..7b1f50fa9dac 100644
>--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
>+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
>@@ -31,8 +31,6 @@
> #include "amdgpu_atomfirmware.h"
> #include "amdgpu_gem.h"
>
>-#include "hdp/hdp_4_0_offset.h"
>-#include "hdp/hdp_4_0_sh_mask.h"
> #include "gc/gc_9_0_sh_mask.h"
> #include "dce/dce_12_0_offset.h"
> #include "dce/dce_12_0_sh_mask.h"
>@@ -1571,7 +1569,6 @@ static int gmc_v9_0_hw_init(void *handle)
> struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> bool value;
> int r, i;
>- u32 tmp;
>
> /* The sequence of these two function calls matters.*/
> gmc_v9_0_init_golden_registers(adev);
>@@ -1590,24 +1587,10 @@ static int gmc_v9_0_hw_init(void *handle)
> if (adev->mmhub.funcs->update_power_gating)
> adev->mmhub.funcs->update_power_gating(adev, true);
>
>- switch (adev->asic_type) {
>- case CHIP_ARCTURUS:
>- WREG32_FIELD15(HDP, 0, HDP_MMHUB_CNTL, HDP_MMHUB_GCC,
>1);
>- break;
>- default:
>- break;
>- }
>-
>- WREG32_FIELD15(HDP, 0, HDP_MISC_CNTL, FLUSH_INVALIDATE_CACHE,
>1);
>-
>- tmp = RREG32_SOC15(HDP, 0, mmHDP_HOST_PATH_CNTL);
>- WREG32_SOC15(HDP, 0, mmHDP_HOST_PATH_CNTL, tmp);
>-
>- WREG32_SOC15(HDP, 0, mmHDP_NONSURFACE_BASE, (adev-
>>gmc.vram_start >> 8));
>- WREG32_SOC15(HDP, 0, mmHDP_NONSURFACE_BASE_HI, (adev-
>>gmc.vram_start >> 40));
>+ adev->hdp.funcs->init_registers(adev);
>
> /* After HDP is initialized, flush HDP.*/
>- adev->nbio.funcs->hdp_flush(adev, NULL);
>+ adev->hdp.funcs->flush_hdp(adev, NULL);
>
> if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS)
> value = false;
>diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c
>b/drivers/gpu/drm/amd/amdgpu/soc15.c
>index 0d3def7269bb..6426ecd1861b 100644
>--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
>+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
>@@ -40,8 +40,6 @@
> #include "gc/gc_9_0_sh_mask.h"
> #include "sdma0/sdma0_4_0_offset.h"
> #include "sdma1/sdma1_4_0_offset.h"
>-#include "hdp/hdp_4_0_offset.h"
>-#include "hdp/hdp_4_0_sh_mask.h"
> #include "nbio/nbio_7_0_default.h"
> #include "nbio/nbio_7_0_offset.h"
> #include "nbio/nbio_7_0_sh_mask.h"
>@@ -59,6 +57,7 @@
> #include "nbio_v6_1.h"
> #include "nbio_v7_0.h"
> #include "nbio_v7_4.h"
>+#include "hdp_v4_0.h"
> #include "vega10_ih.h"
> #include "vega20_ih.h"
> #include "navi10_ih.h"
>@@ -84,14 +83,6 @@
> #define mmMP0_MISC_LIGHT_SLEEP_CTRL
>0x01ba
> #define mmMP0_MISC_LIGHT_SLEEP_CTRL_BASE_IDX
>0
>
>-/* for Vega20 register name change */
>-#define mmHDP_MEM_POWER_CTRL 0x00d4
>-#define HDP_MEM_POWER_CTRL__IPH_MEM_POWER_CTRL_EN_MASK
>0x00000001L
>-#define HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK
>0x00000002L
>-#define HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN_MASK
>0x00010000L
>-#define HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK
>0x00020000L
>-#define mmHDP_MEM_POWER_CTRL_BASE_IDX 0
>-
> /*
> * Indirect registers accessor
> */
>@@ -700,6 +691,7 @@ int soc15_set_ip_blocks(struct amdgpu_device *adev)
> adev->nbio.funcs = &nbio_v6_1_funcs;
> adev->nbio.hdp_flush_reg = &nbio_v6_1_hdp_flush_reg;
> }
>+ adev->hdp.funcs = &hdp_v4_0_funcs;
>
> if (adev->asic_type == CHIP_VEGA20 || adev->asic_type ==
>CHIP_ARCTURUS)
> adev->df.funcs = &df_v3_6_funcs; @@ -835,21 +827,6 @@ int
>soc15_set_ip_blocks(struct amdgpu_device *adev)
> return 0;
> }
>
>-static void soc15_flush_hdp(struct amdgpu_device *adev, struct
>amdgpu_ring *ring) -{
>- adev->nbio.funcs->hdp_flush(adev, ring);
>-}
>-
>-static void soc15_invalidate_hdp(struct amdgpu_device *adev,
>- struct amdgpu_ring *ring)
>-{
>- if (!ring || !ring->funcs->emit_wreg)
>- WREG32_SOC15_NO_KIQ(HDP, 0,
>mmHDP_READ_CACHE_INVALIDATE, 1);
>- else
>- amdgpu_ring_emit_wreg(ring, SOC15_REG_OFFSET(
>- HDP, 0, mmHDP_READ_CACHE_INVALIDATE), 1);
>-}
>-
> static bool soc15_need_full_reset(struct amdgpu_device *adev) {
> /* change this when we implement soft reset */ @@ -858,10 +835,7 @@
>static bool soc15_need_full_reset(struct amdgpu_device *adev)
>
> static void vega20_reset_hdp_ras_error_count(struct amdgpu_device
>*adev) {
>- if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__HDP))
>- return;
>- /*read back hdp ras counter to reset it to 0 */
>- RREG32_SOC15(HDP, 0, mmHDP_EDC_CNT);
>+ adev->hdp.funcs->reset_ras_error_count(adev);
> }
>
> static void soc15_get_pcie_usage(struct amdgpu_device *adev, uint64_t
>*count0, @@ -1012,8 +986,6 @@ static const struct amdgpu_asic_funcs
>soc15_asic_funcs =
> .set_uvd_clocks = &soc15_set_uvd_clocks,
> .set_vce_clocks = &soc15_set_vce_clocks,
> .get_config_memsize = &soc15_get_config_memsize,
>- .flush_hdp = &soc15_flush_hdp,
>- .invalidate_hdp = &soc15_invalidate_hdp,
> .need_full_reset = &soc15_need_full_reset,
> .init_doorbell_index = &vega10_doorbell_index_init,
> .get_pcie_usage = &soc15_get_pcie_usage, @@ -1035,8 +1007,6 @@
>static const struct amdgpu_asic_funcs vega20_asic_funcs =
> .set_uvd_clocks = &soc15_set_uvd_clocks,
> .set_vce_clocks = &soc15_set_vce_clocks,
> .get_config_memsize = &soc15_get_config_memsize,
>- .flush_hdp = &soc15_flush_hdp,
>- .invalidate_hdp = &soc15_invalidate_hdp,
> .reset_hdp_ras_error_count = &vega20_reset_hdp_ras_error_count,
Could you remove this asic function also ? You may use this check before calling hdp reset errors function.
if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__HDP))
Regards,
Lijo
> .need_full_reset = &soc15_need_full_reset,
> .init_doorbell_index = &vega20_doorbell_index_init, @@ -1422,41
>+1392,6 @@ static int soc15_common_soft_reset(void *handle)
> return 0;
> }
>
>-static void soc15_update_hdp_light_sleep(struct amdgpu_device *adev,
>bool enable) -{
>- uint32_t def, data;
>-
>- if (adev->asic_type == CHIP_VEGA20 ||
>- adev->asic_type == CHIP_ARCTURUS ||
>- adev->asic_type == CHIP_RENOIR) {
>- def = data = RREG32(SOC15_REG_OFFSET(HDP, 0,
>mmHDP_MEM_POWER_CTRL));
>-
>- if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS))
>- data |=
>HDP_MEM_POWER_CTRL__IPH_MEM_POWER_CTRL_EN_MASK |
>-
>HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK |
>-
>HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN_MASK |
>-
>HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK;
>- else
>- data &=
>~(HDP_MEM_POWER_CTRL__IPH_MEM_POWER_CTRL_EN_MASK |
>-
>HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK |
>-
>HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN_MASK |
>-
>HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK);
>-
>- if (def != data)
>- WREG32(SOC15_REG_OFFSET(HDP, 0,
>mmHDP_MEM_POWER_CTRL), data);
>- } else {
>- def = data = RREG32(SOC15_REG_OFFSET(HDP, 0,
>mmHDP_MEM_POWER_LS));
>-
>- if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS))
>- data |= HDP_MEM_POWER_LS__LS_ENABLE_MASK;
>- else
>- data &= ~HDP_MEM_POWER_LS__LS_ENABLE_MASK;
>-
>- if (def != data)
>- WREG32(SOC15_REG_OFFSET(HDP, 0,
>mmHDP_MEM_POWER_LS), data);
>- }
>-}
>-
> static void soc15_update_drm_clock_gating(struct amdgpu_device *adev,
>bool enable) {
> uint32_t def, data;
>@@ -1517,7 +1452,7 @@ static int
>soc15_common_set_clockgating_state(void *handle,
> state == AMD_CG_STATE_GATE);
> adev->nbio.funcs->update_medium_grain_light_sleep(adev,
> state == AMD_CG_STATE_GATE);
>- soc15_update_hdp_light_sleep(adev,
>+ adev->hdp.funcs->update_clock_gating(adev,
> state == AMD_CG_STATE_GATE);
> soc15_update_drm_clock_gating(adev,
> state == AMD_CG_STATE_GATE); @@ -1534,7 +1469,7 @@
>static int soc15_common_set_clockgating_state(void *handle,
> state == AMD_CG_STATE_GATE);
> adev->nbio.funcs->update_medium_grain_light_sleep(adev,
> state == AMD_CG_STATE_GATE);
>- soc15_update_hdp_light_sleep(adev,
>+ adev->hdp.funcs->update_clock_gating(adev,
> state == AMD_CG_STATE_GATE);
> soc15_update_drm_clock_gating(adev,
> state == AMD_CG_STATE_GATE); @@ -1542,7 +1477,7 @@
>static int soc15_common_set_clockgating_state(void *handle,
> state == AMD_CG_STATE_GATE);
> break;
> case CHIP_ARCTURUS:
>- soc15_update_hdp_light_sleep(adev,
>+ adev->hdp.funcs->update_clock_gating(adev,
> state == AMD_CG_STATE_GATE);
> break;
> default:
>@@ -1561,10 +1496,7 @@ static void
>soc15_common_get_clockgating_state(void *handle, u32 *flags)
>
> adev->nbio.funcs->get_clockgating_state(adev, flags);
>
>- /* AMD_CG_SUPPORT_HDP_LS */
>- data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS));
>- if (data & HDP_MEM_POWER_LS__LS_ENABLE_MASK)
>- *flags |= AMD_CG_SUPPORT_HDP_LS;
>+ adev->hdp.funcs->get_clock_gating_state(adev, flags);
>
> /* AMD_CG_SUPPORT_DRM_MGCG */
> data = RREG32(SOC15_REG_OFFSET(MP0, 0,
>mmMP0_MISC_CGTT_CTRL0));
>--
>2.25.1
>
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