[PATCH] drm/amd/display: Indicate use of TMZ buffers to DC
Kazlauskas, Nicholas
nicholas.kazlauskas at amd.com
Thu Feb 6 16:58:42 UTC 2020
On 2020-02-06 11:54 a.m., Bhawanpreet Lakha wrote:
> From: Harry Wentland <harry.wentland at amd.com>
>
> [Why]
> Hubp needs to know whether a buffer is being scanned out from the trusted
> memory zone or not.
>
> [How]
> Check for the TMZ flag on the amdgpu_bo and set the tmz_surface flag in
> dc_plane_address accordingly.
>
> Signed-off-by: Harry Wentland <harry.wentland at amd.com>
> Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha at amd.com>
> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha at amd.com>
Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas at amd.com>
> ---
> .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 38 +++++++++++++------
> 1 file changed, 27 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> index 7f6d3b0f9efc..73000f1e1734 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> @@ -3166,7 +3166,7 @@ static int fill_dc_scaling_info(const struct drm_plane_state *state,
> }
>
> static int get_fb_info(const struct amdgpu_framebuffer *amdgpu_fb,
> - uint64_t *tiling_flags)
> + uint64_t *tiling_flags, bool *tmz_surface)
> {
> struct amdgpu_bo *rbo = gem_to_amdgpu_bo(amdgpu_fb->base.obj[0]);
> int r = amdgpu_bo_reserve(rbo, false);
> @@ -3181,6 +3181,9 @@ static int get_fb_info(const struct amdgpu_framebuffer *amdgpu_fb,
> if (tiling_flags)
> amdgpu_bo_get_tiling_flags(rbo, tiling_flags);
>
> + if (tmz_surface)
> + *tmz_surface = amdgpu_bo_encrypted(rbo);
> +
> amdgpu_bo_unreserve(rbo);
>
> return r;
> @@ -3263,7 +3266,8 @@ fill_plane_buffer_attributes(struct amdgpu_device *adev,
> union dc_tiling_info *tiling_info,
> struct plane_size *plane_size,
> struct dc_plane_dcc_param *dcc,
> - struct dc_plane_address *address)
> + struct dc_plane_address *address,
> + bool tmz_surface)
> {
> const struct drm_framebuffer *fb = &afb->base;
> int ret;
> @@ -3273,6 +3277,8 @@ fill_plane_buffer_attributes(struct amdgpu_device *adev,
> memset(dcc, 0, sizeof(*dcc));
> memset(address, 0, sizeof(*address));
>
> + address->tmz_surface = tmz_surface;
> +
> if (format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) {
> plane_size->surface_size.x = 0;
> plane_size->surface_size.y = 0;
> @@ -3461,7 +3467,8 @@ fill_dc_plane_info_and_addr(struct amdgpu_device *adev,
> const struct drm_plane_state *plane_state,
> const uint64_t tiling_flags,
> struct dc_plane_info *plane_info,
> - struct dc_plane_address *address)
> + struct dc_plane_address *address,
> + bool tmz_surface)
> {
> const struct drm_framebuffer *fb = plane_state->fb;
> const struct amdgpu_framebuffer *afb =
> @@ -3540,7 +3547,7 @@ fill_dc_plane_info_and_addr(struct amdgpu_device *adev,
> plane_info->rotation, tiling_flags,
> &plane_info->tiling_info,
> &plane_info->plane_size,
> - &plane_info->dcc, address);
> + &plane_info->dcc, address, tmz_surface);
> if (ret)
> return ret;
>
> @@ -3563,6 +3570,7 @@ static int fill_dc_plane_attributes(struct amdgpu_device *adev,
> struct dc_plane_info plane_info;
> uint64_t tiling_flags;
> int ret;
> + bool tmz_surface = false;
>
> ret = fill_dc_scaling_info(plane_state, &scaling_info);
> if (ret)
> @@ -3573,13 +3581,14 @@ static int fill_dc_plane_attributes(struct amdgpu_device *adev,
> dc_plane_state->clip_rect = scaling_info.clip_rect;
> dc_plane_state->scaling_quality = scaling_info.scaling_quality;
>
> - ret = get_fb_info(amdgpu_fb, &tiling_flags);
> + ret = get_fb_info(amdgpu_fb, &tiling_flags, &tmz_surface);
> if (ret)
> return ret;
>
> ret = fill_dc_plane_info_and_addr(adev, plane_state, tiling_flags,
> &plane_info,
> - &dc_plane_state->address);
> + &dc_plane_state->address,
> + tmz_surface);
> if (ret)
> return ret;
>
> @@ -5174,6 +5183,7 @@ static int dm_plane_helper_prepare_fb(struct drm_plane *plane,
> uint64_t tiling_flags;
> uint32_t domain;
> int r;
> + bool tmz_surface = false;
>
> dm_plane_state_old = to_dm_plane_state(plane->state);
> dm_plane_state_new = to_dm_plane_state(new_state);
> @@ -5222,6 +5232,8 @@ static int dm_plane_helper_prepare_fb(struct drm_plane *plane,
>
> amdgpu_bo_get_tiling_flags(rbo, &tiling_flags);
>
> + tmz_surface = amdgpu_bo_encrypted(rbo);
> +
> ttm_eu_backoff_reservation(&ticket, &list);
>
> afb->address = amdgpu_bo_gpu_offset(rbo);
> @@ -5236,7 +5248,7 @@ static int dm_plane_helper_prepare_fb(struct drm_plane *plane,
> adev, afb, plane_state->format, plane_state->rotation,
> tiling_flags, &plane_state->tiling_info,
> &plane_state->plane_size, &plane_state->dcc,
> - &plane_state->address);
> + &plane_state->address, tmz_surface);
> }
>
> return 0;
> @@ -6417,6 +6429,7 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
> unsigned long flags;
> struct amdgpu_bo *abo;
> uint64_t tiling_flags;
> + bool tmz_surface = false;
> uint32_t target_vblank, last_flip_vblank;
> bool vrr_active = amdgpu_dm_vrr_active(acrtc_state);
> bool pflip_present = false;
> @@ -6515,12 +6528,14 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
>
> amdgpu_bo_get_tiling_flags(abo, &tiling_flags);
>
> + tmz_surface = amdgpu_bo_encrypted(abo);
> +
> amdgpu_bo_unreserve(abo);
>
> fill_dc_plane_info_and_addr(
> dm->adev, new_plane_state, tiling_flags,
> &bundle->plane_infos[planes_count],
> - &bundle->flip_addrs[planes_count].address);
> + &bundle->flip_addrs[planes_count].address, tmz_surface);
>
> bundle->surface_updates[planes_count].plane_info =
> &bundle->plane_infos[planes_count];
> @@ -7889,6 +7904,7 @@ dm_determine_update_type_for_commit(struct amdgpu_display_manager *dm,
> struct dc_flip_addrs *flip_addr = &bundle->flip_addrs[num_plane];
> struct dc_scaling_info *scaling_info = &bundle->scaling_infos[num_plane];
> uint64_t tiling_flags;
> + bool tmz_surface = false;
>
> new_plane_crtc = new_plane_state->crtc;
> new_dm_plane_state = to_dm_plane_state(new_plane_state);
> @@ -7934,14 +7950,14 @@ dm_determine_update_type_for_commit(struct amdgpu_display_manager *dm,
> bundle->surface_updates[num_plane].scaling_info = scaling_info;
>
> if (amdgpu_fb) {
> - ret = get_fb_info(amdgpu_fb, &tiling_flags);
> + ret = get_fb_info(amdgpu_fb, &tiling_flags, &tmz_surface);
> if (ret)
> goto cleanup;
>
> ret = fill_dc_plane_info_and_addr(
> dm->adev, new_plane_state, tiling_flags,
> - plane_info,
> - &flip_addr->address);
> + &plane_info,
> + &flip_addr.address, tmz_surface);
> if (ret)
> goto cleanup;
>
>
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