[PATCH] drm/amdgpu/soc15: fix xclk for raven

[Quan, Evan]

Acked-by: Evan Quan <evan.quan at amd.com>

> -----Original Message-----
> From: amd-gfx <amd-gfx-bounces at lists.freedesktop.org> On Behalf Of Alex
> Deucher
> Sent: Wednesday, February 12, 2020 2:51 PM
> To: amd-gfx at lists.freedesktop.org
> Cc: Deucher, Alexander <Alexander.Deucher at amd.com>
> Subject: [PATCH] drm/amdgpu/soc15: fix xclk for raven
> 
> It's 25 Mhz (refclk / 4).  This fixes the interpretation
> of the rlc clock counter.
> 
> Signed-off-by: Alex Deucher <alexander.deucher at amd.com>
> ---
>  drivers/gpu/drm/amd/amdgpu/soc15.c | 7 ++++++-
>  1 file changed, 6 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c
> b/drivers/gpu/drm/amd/amdgpu/soc15.c
> index 15f3424a1ff7..2b488dfb2f21 100644
> --- a/drivers/gpu/drm/amd/amdgpu/soc15.c
> +++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
> @@ -272,7 +272,12 @@ static u32 soc15_get_config_memsize(struct
> amdgpu_device *adev)
> 
>  static u32 soc15_get_xclk(struct amdgpu_device *adev)
>  {
> -	return adev->clock.spll.reference_freq;
> +	u32 reference_clock = adev->clock.spll.reference_freq;
> +
> +	if (adev->asic_type == CHIP_RAVEN)
> +		return reference_clock / 4;
> +
> +	return reference_clock;
>  }
> 
> 
> --
> 2.24.1
> 
> _______________________________________________
> amd-gfx mailing list
> amd-gfx at lists.freedesktop.org
> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.
> freedesktop.org%2Fmailman%2Flistinfo%2Famd-
> gfx&data=02%7C01%7Cevan.quan%40amd.com%7Cc6edc950af7441901
> e4308d7af87f4a9%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C63
> 7170870805268030&sdata=CCDroHD1H5m8ak0zsCg4KXi3Sf6f8yVY31xdM
> 0wcyzw%3D&reserved=0