[PATCH] drm/amd/amdgpu: Add gfxoff debugfs entry

[Alex Deucher]

On Mon, Feb 24, 2020 at 9:41 AM Tom St Denis <tom.stdenis at amd.com> wrote:
>
>
> On 2020-02-21 1:59 p.m., Alex Deucher wrote:
> > On Fri, Feb 21, 2020 at 1:45 PM Tom St Denis <tom.stdenis at amd.com> wrote:
> >> Write a 32-bit value of zero to disable GFXOFF and write a 32-bit
> >> value of non-zero to enable GFXOFF.
> >>
> >> Signed-off-by: Tom St Denis <tom.stdenis at amd.com>
> >> ---
> >>   drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c | 56 +++++++++++++++++++++
> >>   1 file changed, 56 insertions(+)
> >>
> >> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
> >> index 7379910790c9..3bb74056b9d2 100644
> >> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
> >> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
> >> @@ -842,6 +842,55 @@ static ssize_t amdgpu_debugfs_gpr_read(struct file *f, char __user *buf,
> >>          return result;
> >>   }
> >>
> >> +/**
> >> + * amdgpu_debugfs_regs_gfxoff_write - Enable/disable GFXOFF
> >> + *
> >> + * @f: open file handle
> >> + * @buf: User buffer to write data from
> >> + * @size: Number of bytes to write
> >> + * @pos:  Offset to seek to
> >> + *
> >> + * Write a 32-bit zero to disable or a 32-bit non-zero to enable
> >> + */
> >> +static ssize_t amdgpu_debugfs_gfxoff_write(struct file *f, const char __user *buf,
> >> +                                        size_t size, loff_t *pos)
> >> +{
> >> +       struct amdgpu_device *adev = file_inode(f)->i_private;
> >> +       ssize_t result = 0;
> >> +       int r;
> >> +
> >> +       if (size & 0x3 || *pos & 0x3)
> >> +               return -EINVAL;
> >> +
> >> +       r = pm_runtime_get_sync(adev->ddev->dev);
> > Not really directly related to this patch, but If you are using umr
> > for debugging, we should probably disable runtime pm, otherwise the
> > entire GPU may be powered down between accesses.  There is already an
> > interface to do that via the core kernel power subsystem in sysfs.
> > E.g.,
> > /sys/class/drm/card0/device/power/control
> > /sys/class/drm/card0/device/power/runtime_status
> > Something else to look at for umr.
>
> We ran into something related to this for UVD/VCE access back in the
> day.  When powered down the MMIO registers are mirrored and accessible
> but while in transition they are not.  So we added a PG flag to the
> offset in the debugfs entry to flag when we need to take the pm mutex or
> not.
>
>
>
>
> >
> > We don't store the state for when we dynamically turn it off like this
> > so if we get a GPU reset or a power management event (runtime pm or
> > S3), GFXOFF will be re-enabled at that point.  This is just for
> > debugging though so:
> > Acked-by: Alex Deucher <alexander.deucher at amd.com>
>
> Good to note.  Can I get a R-b from someone though so I can push this out?

You can convert mine to an RB if you prefer.

Alex

>
>
> Tom
>